K. Lahiri, A. Raghunathan, G. Lakshminarayana, and S. Dey, "Communication Architecture Tuners: A Methodology for the Design of High-Performance Communication Architectures for System-on-Chips", Proc. Design Automation Conf., pp. 513--518, June 2000.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....is done with a top level TDMA system that has slices open for dynamic tasks. This paper does not specify how the arbitration occurs in the dynamic slots, and is not as flexible as STRANG, which can express schedules with arbitrary levels of hierarchy. Dey s Communication Architecture Tuners in [10] has been a source of inspiration for this paper. Controllers are synthesized that base bus arbitration on certain properties of the messages. An example that is unschedulable using static priorities, is actually scheduled making the arbitration policy a function of multiple message ....

....end of transmission times making it easy to calculate the quality of the results according to an appropriate fitness function. In section 5.1.4, we will show how to use the analysis to improve the scheduling policy. We are exploring the use of automatic techniques such as the tracer tokens from [10] and genetic algorithms to aid in the exploration of the design space. 5. EXPERIMENTAL RESULTS In this section, we provide a set of examples that have been run using the tool. We begin by evaluating CAN and TTP solutions to the SAE automotive control benchmark. From here, we optimize both ....

K. Lahiri, A. Raghunathan, G. Lakshminarayana, and S. Dey. Communication architecture tuners: a methodology for the design of high-performance communication architectures for system-on-chips. In Design Automation Conference, pages 513--18. IEEE, June 2000.

....compared to the simulation using instruction set simulators for SW simulation. 1 Introduction Communication refinement is a crucial design step in System on Chip (SoC) design since it has significant impact on the performance of implemented SoCs in terms of power consumption, runtime, area, etc. [1]. Communication refinement consists of two steps: communication network design and wrapper design. Communication network can be on chip buses [2] 3] circuit switch networks [4] packet switch networks [5] 6] etc. Wrappers are required to adapt modules to communication networks. Wrappers are ....

K. Lahiri, A. Raghunathan, G. Lakshminarayana, and S. Dey, "Communication Architecture Tuners: A Methodology for the Design of High-Performance Communication Architectures for System-onChips ", Proc. Design Automation Conf., pp. 513--518, June 2000.

....platform which they tune for power, they do not consider the cost of the architecture as a metric. Drinic et al. 18] present an onchip bus network design methodology, optimizing the allocation of the cores to busses to reduce the latency of the transfers across the busses. Lahiri et al. [17] present a methodology for the design of custom System on Chip communication architectures, which propose the use of dynamic reconfiguration of the communication characteristics, taking into account the needs of the application. III) Recent work on interface synthesis [4] 5] present techniques ....

K. Lahiri, A Raghunatan, G. Lakshminarayana, and S. Dey. Communication architecture tuners: A methodology for hte deisng of high-performance communication architectures for systems-on-chip. In DAC, 2000.

....an extended shared memory model. Experiments show the effectiveness of the proposed method. 1 Introduction As communication architectures of 1P based systems, shared bus architectures are widely used in many 1P based systems. Recently, research on performance estimation [1] 2] and optimization [3] of such communication architectures are gaining more and more attention. In shared bus architectures, since performance bottleneck comes mostly from excessive bus conflicts, placing data caches near IP cores can give significant improvement of system performance by reducing bus conflicts. In such ....

K. Lahiri, A. Raghunathan, G. Lakshminarayana, and S. Dey, "Communication Architecture Tuners: A Methodology for the Design of High-Performance Communication Architectures for System-on-Chips", Proc. Design Automation Cot, June 2000.

....data network on a chip is not new many networking chips integrate a switch fabric to accomplish the routing function. Some have proposed similar communication architectures for SOCs [3] Chang [4] provides a reasonable survey of the available communications topologies and protocols, and Lahiri [5] proposes a novel dynamic scheme for optimizing existing protocols. Rowson [6] presents a compelling case for separating the functionality of an IP core from its communications. The Virtual Socket Interface Alliance s On Chip Bus activity has produced a specification for an ....

K. Lahiri et al., "Communications Architecture Tuners: A Methodology for the Design of High-Performance Communication Architectures for Systems-on-Chip," in Proc. of the 37 Design Automation Conference, pp. 513518, June 2000.

....CDMA cellular phone system. 1 Introduction In designing embedded multi processor SoCs (systems on chip) communication refinement is one of crucial tasks since the communication implementation can have significant impact on system performance in terms of runtime, area, power consumption, etc. [1][2] 3] It is also a challenging task since complex functional and communication requirements of current embedded SoCs require application specific processors (e.g. CPU s, DSP s, IP s, etc. and high performance complex communication networks (e.g. giga bytelevel communication bandwidth, ....

....or (2) an internal bus (when it is at RT level) Details of abstraction levels and ICM will be presented in Section 3.2 and Section 4, respectively. 2.3 Our Contribution Compared with related work, our contribution is as follows. Comparing with optimization techniques in communication refinement [1][2] 3] our work is complimentary to them since wrapper generation (for simulation and or synthesis) is a part of architecture generation that is performed after the communication architecture and the parameters of communication (e.g. the architecture of onchip bus, the priority of bus access, ....

K. Lahiri, A. Raghunathan, G. Lakshminarayana, and S. Dey, "Communication Architecture Tuners: A Methodology for the Design of High-Performance Communication Architectures for System-on-Chips", Proc. Design Automation Conf., pp. 513--518, June 2000.

....speedup compared to the simulation using instruction set simulators for SW simulation. 1 Introduction Communication refinement is a crucial design step in System onChip (SoC) design since it has significant impact on the performance of implemented SoCs in terms of power, runtime, area, etc. [1]. Communication refinement consists of two steps: communication network design and wrapper design. Communication network can be on chip buses [2] circuit switch networks, packet switch networks, etc. Wrappers are required for communication between applications running on different processors, ....

K. Lahiri, A. Raghunathan, G. Lakshminarayana, and S. Dey, "Communication Architecture Tuners: A Methodology for the Design of High-Performance Communication Architectures for System-on-Chips", Proc. Design Automation Conf., pp. 513--518, June 2000.

....and PCI bus arbitration between nodes. This simple scheme performs well since all communication in Spar Java is part of a collective operation that ends after all data transfers are completed. Hence, the order does not matter. More advanced schemes may be used for non collective communication. In [7], for example, an approach is described that monitors the system and dynamically predicts the importance of individual data transfers and assigns communication priorities accordingly. In the way it is used, ensemble resembles irregular communication libraries such as CHAOS [11] In both cases a ....

K. Lahiri, G. Lakshminarayana, A. Raghunathan, and S. Dey. Communication architecture tuners: A methodology for the design of high performance communication architectures. In 37th Design Automation Conference (DAC2000), Los Angeles, CA, June 2000.

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K. Lahiri, A. Raghunathan, G. Lakshminarayana, and S. Dey, "Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips," in Proc. Design Automation Conf., pp. 513--518, June 2000.

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K. Lahiri, A. Raghunathan, G. Lakshminarayana, andS . Dey, "Communication architecture tuners: A methodology for the design of high performance communication architectures for system-on-chips," in Proc. Desi, Automati) Conf., June 2000, pp. 513--518.

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K. Lahiri, A. Raghunathan, G. Lakshminarayana, and S. Dey, "Communication Architecture Tuners: A Methodology for the Design of High-Performance Communication Architectures for System-on-Chips", Proc. Design Automation Conf., pp. 513--518, June 2000.

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K. Lahiri, A. Raghunathan, G. Lakshminarayana, S. Dey, "Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chip," IEEE/ACM Design Automation Conference, pp. 513--518, 2000.

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