Ku D. and De Micheli G., "HardwareC: A Language for Hardware Design", Stanford University Technical Report CSLTR -90-419 (1990), Version 2.0.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....[6] Our approach is di erent in that it displays an asynchronous communication model at design level, while generating a synchronous implementation. Another approach uses software languages such as C and C . The Olympus Hercules system is designed to support mainly ASIC synthesis from HardwareC [17], a C like syntax behavioral language. HardwareC supports concurrency by providing synchronous queues with blocking send and receive constructs. In Scenic [9] the semantics of concurrency is similar to that of CSP and processes communicate via signals. In both approaches, the synchronous ....

D. Ku and G. De Micheli. HardwareC: a language for hardware design. Technical Report SCSL/CSL/TR-90-419, Computer Systems Laboratory, Stanford Univ., Stanford, Calif., August 1990.

....tool. Another possibility is to trade hardware with time. In this case a single hardware block can be used to compute sequentially the value of several internal variables. This mapping is less direct and requires a more complex soft, rare for high level synthesis such as those described in [2] [9]. The second part of the synthesis tool is similar to the synthesis tools used today to map RTL descriptions on FPGAs. A third part of the tool will determine, following the specification of the user, how many modules of each type will be mapped in the nanonetwork and how they will be distributed ....

....on the software mapping tool. Also, initial reflection was conducted on the hardware exploration domain but no tool development have been conducted. Finally, no developments were conducted in the synthesis tool. But the approach is similar to existing EDA tools performing high level synthesis [2] [9]and to those mapping RTL descriptions into FPGAs [10] 15] 4. The software mapping tool To avoid developing this tool on the basis of abstract considerations, which could result in an unrealistic system, we need a case study application. This application should include all the constraints that ....

Ku, D.C. and De Micheli, D.: HardwareC - A Language for Hardware Design. Stanford University, Technical Report CSL-TR-90-419, 1988.

....day computer technologies and then use derivative metrics (such as miss rate) to extrapolate potential benefits for future computer systems which will exhibit much higher clock rates and memory sizes. We also manually translated the C routines modeling the customizable logic blocks into HardwareC [41] to evaluate their hardware cost in terms of size and cycle delays. Our recent work is focused on automatic translation of these routines to synthesizable blocks [45] 6.2.1 Architectural Adaptation for Latency Tolerance Our first case study uses architectural adaptation for prefetching. As ....

Ku, D., and Micheli, G. D. HardwareC - A Language for Hardware Design (version 2.0). CSL Technical Report CSL-TR-90-419, Stanford University, Apr. 1990.

....out by Mercury and technology mapping is the job of Ceres. Since this thesis is only concerned with high level synthesis we choose to focus only on Hercules and Hebe. 2.2. 1 The HardwareC Language The input to Olympus is a behavioural specification written in a language called HardwareC [87]. Although the language has a C like syntax this is where the similarity with C [84] ends. HardwareC supports four fundamental design abstractions: Abstraction Description block A structural block parameterised over input output ports. The body of a block contains instantiations of other blocks ....

....source to source transformations (Section 4. 4) Note that although, for expository purposes, this chapter describes Soft Scheduling in the framework of SAFL, the technique is applicable to any high level HDL which allows function definitions to be treated as shared resources (e.g. HardwareC [87], Balsa [45] Tangram [139] Indeed, in Chapter 7 we extend SAFL with # calculus [101] style channels and assignment and demonstrate that the Soft Scheduling technique scales accordingly. Traditional high level synthesis packages perform scheduling using a data structure called a sequencing ....

KU, D., AND DE MICHELI, G. HardwareC---a language for hardware design (version 2.0). Tech. Rep. CSL-TR-90-419, Stanford University, 1990.

....operation is unconditionally called on the completion of the sink operation. The IDR consists of a set F = G 1 , G 2 , G n of FGMs, a set of timing constraints (T ) and a set of resource constraints (R ) This IDR is used in the VULCAN system [47] where a HardwareC specification [62] is translated into FGM by a program called Hercules [61] SPI The System Property Intervals (SPI) model consist of processes communicating through unidirectional channels, which are defined in terms of a tuple #P,C,E#, where P is a set of processes, C = Q#R is a set of channels (composed of ....

David Ku and Giovanni De Micheli. HardwareC -- A language for hardware design (version 2.0). Technical Report CSL-TR-90-419, Stanford University, Computer Systems Laboratory, 1990. 45

....System for HLS [20] and then this became part of the Vulcan 1 framework. The problem has been clearly formulated [33] and a description of the target architecture addressed by this group can be found in [31] which its by itself an extension of [33] Specifications are given in HardwareC [41], a HDL developed in Stanford University by late 80s, and then compiled into a sequencing graph model (SGM) 35] a graph representation based on flow graphs [19] using the program Hercules [42] The system behaviour is represented by a set of acyclic sequencing graphs (# = G 1 , G 2 , ....

D. Ku and G. De Micheli. HardwareC -- A language for hardware design (version 2.0). Technical Report CSL-TR-90-419, Stanford University, Computer Systems Laboratory, 1990.

....Our approach is different in that it displays an asynchronous communication model at design level, while generating a synchronous implementation. Another approach uses software languages, such as C and C . The Olympus Hercules system is designed to support mainly ASIC synthesis from HardwareC [15], a C like syntax behavioral language. HardwareC supports concurrency by providing synchronous queues with blocking send and receive constructs. In Scenic [9] the semantics of concurrency is similar to that of CSP and processes communicate via signals. In both approaches, the synchronous ....

D. Ku and G. De Micheli. HardwareC: a language for hardware design. Technical Report SCSL/CSL/TR-90-419, Computer Systems Laboratory, Stanford Univ., Stanford, Calif., August 1990.

....information, redesign is greatly simplified. Little or no reverse engineering is required to determine an existing design s behavior before modifying it for another application. A variety of languages have been proposed for behavioral specification, such as VHDL [1] Verilog [2] HardwareC [3], CSP [4] and Statecharts [5] A good language should support a conceptual model useful for the particular system to be specified. For example, C supports an object oriented conceptual model which has proven useful for many large software systems. A language should also be able to represent a ....

....note that VHDL processes repeat infinitely so do not have a defined completion. 2.5 Limitations of other specification languages Several other languages have been developed for behavior specification, but none support all five of the embedded system characteristics outlined above. HardwareC [3] extends the sequential programming paradigm with concurrent processes, so it shares the same problems as VHDL. Verilog [2] extends the sequential programming paradigm with two additional constructs, fork join and behavior disable, which support activity decomposition and immediate mode change. ....

D. Ku and G. Micheli, "HardwareC - A Language for Hardware Design." Stanford University, Technical ReportCSL-TR-90-419, 1988.

....as both the input and output format [vEdJS91] For some time now, it has been clear that, if the products of the research effort in the ASCIS project are ever to be accepted and used by the industry, it must be possible to describe the DFGs in a high level language. Up to now, only HardwareC [KD88] and Darmstadt C [thh] have been supported. This thesis describes the advent of a new compiler, which translates VHDL into an ASCIS DFG. The reader is assumed to be at least slightly familiar with VHDL [Ins88] the ASCIS DFG [vEdJS91, vES92] the concepts of architectural synthesis [JTJ 92] ....

D.C. Ku and G. DeMicheli. HardwareC---A Language for Hardware Design. Technical Report CSL--TR--88--362, Stanford, August 1988.

....input character is received from the MAIN module, padded with start and stop bits and shifted out serially (least significant bit first) on the TxD output at a rate determined by the baud rate setting in the mode word. 4. 5 Comparison With Existing Work Intel 8251 has been specified in HardwareC [25] and a variant of ISPS [42] The specifications are available with the distribution of high level synthesis benchmarks. In this section we will compare the hopCP specification of the 8251 with its HardwareC and ISPS specifications. We will also touch 20 VENKATESH AKELLA, GANESH GOPALAKRISHNAN upon ....

....abstraction in the sense that it describes on particular implementation of the 8251, based on synchronization flip flops (ii) does not have constructs to expressing parallel behavior explicitly. iii) the computation is described in a imperative language. 4.5. 2 HardwareC The language hardwareC [25] comes closest to hopCP in terms of the communication constructs it uses. This is encouraging because starting from similar motivations about the real world scenarios that we wish to model, we have independently ended up selecting the same set of communication constructs in our respective HDLs. ....

Ku, D., and Micheli, G. D. HardwareC - A Language for Hardware Design, Version 2.0. Tech. Rep. CSL-TR-90-419, Computer Science Laboratory, Stanford University, April 1990.

....applied in hardware design. Finally, the fact that C is extensible allows designers to create their own class libraries that can be reused to design test benches across various design projects. 2 Previous Work Designing hardware from C is not new. There have been previous efforts in HardwareC [1, 4], OCAPI [6] HandelC [3] and Transmogrifier C [2] Because these efforts used C as their base language, however, they had no natural mechanism to create either the notion of an instance of an object or a hierarchy of objects. Concurrency had to be modeled using message passing mechanisms. With ....

D. Ku and G. De Micheli, HardwareC: A Language for Hardware Design, Technical Report: CSL-TR-90419, Computer System Laboratory, Stanford University August 1990 (Version 2.0)

....is monitored. As a general rule, the higher the level of detail the larger is the computing time consumed. This time can be significant if the simulation is structural where it may vary from 10 to 100 million of gates and this time grows in logarithm scale. Some of these languages are HardwareC [Ku and De Micheli (1988)] VHDL [Lipsett et al. 1989) Statecharts[Drusinsky and Harel (1989) Silage [Hilfinger and Rabey (1992) 1 Universidade Federal de So Carlos So Carlos SP BRAZIL 2 Escola Politcnica da USP So Paulo SP BRAZIL 2 SpecCharts language [Vahid et al. 1991) Verilog [Sternheim et al. ....

- Ku, D. and De Micheli, G. "HardwareC - A Language for Hardware Design" - Stanford University, Technical Report CSL-TR-90-419, 1988. 7

....of HDLs with different objectives and emphasis. The following are some of the hardware description formalisms currently in use: trace theory [19] CSP probe [34] Occam [7] used for the synthesis of pure asynchronous circuits, trace theory [18] for verification of asynchronous circuits, HardwareC [30] and ISPS (with variations) 57] for synthesis of synchronous circuits, functional calculus [26] for synthesis and verification of synchronous circuits, and Verilog HDL [54] and VHDL for modeling and simulation of synchronous and asynchronous circuits. It is difficult to place hopCP in this ....

Ku, D., and Micheli, G. D. HardwareC - A Language for Hardware Design, Version 2.0. Tech. Rep. CSL-TR-90-419, Computer Science Laboratory, Stanford University, April 1990.

....[McFarland 78] that has a higher level construct for specifying timing constraints. Minimum and maximum separation times between system activites are specified using labels attached to program statements. A similar approach 25 (see Figure 2. 4) is used by the more recent language HardwareC [Ku de Micheli 90] tag rd, wr, op; perform tasks rd: data = read(input port) op: result = some function(data) wr: write output port = result; specify timing constraints constraint mintime from rd to op = 3 cycles; constraint maxtime from op to wr = 5 cycles; constraint maxtime from rd to wr = 10 ....

D. Ku and G. de Micheli. HardwareC --- A language for hardware design, version 2.0. Technical Report TR CSL--TR-90-419, Computer Systems Laboratory, Stanford University, April 1990.

....day computer technologies and then use derivative metrics (such as miss rate) to extrapolate potential benefits for future computer systems which will exhibit much higher clock rates and memory sizes. We also manually translated the C routines modeling the customizable logic blocks into HardwareC [18] to evaluate their hardware cost in terms of space and cycle delays. However, our recent work is focused on automatic translation of these routines to synthesizable blocks [19] TABLE I Simulation Parameters L1 Cache L2 Cache Line Size 32B or 64B 32B or 64B Associativity 1 2 Cache Size 32KB ....

Ku, D., and Micheli, G. D. HardwareC - A Language for Hardware Design (version 2.0). CSL Tech. Rep. CSL-TR-90-419, Stanford University, Apr. 1990.

....day computer technologies and then use derivative metrics (such as miss rate) to extrapolate potential benefits for future computer systems which will exhibit much higher clock rates and memory sizes. We also manually translated the C routines modeling the customizable logic blocks into HardwareC [18] to evaluate their hardware cost in terms of space and cycle delays. However, our recent work is focused on automatic translation of these routines to synthesizable blocks [19] L1 Cache L2 Cache Line Size 32B or 64B 32B or 64B Associativity 1 2 Cache Size 32KB 512KB Write Write back Write ....

KU, D., AND MICHELI, G. D. HardwareC - A Language for Hardware Design (version 2.0). CSL Tech. Rep. CSL-TR-90-419, Stanford Univ., Apr. 1990.

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Ku D. and De Micheli G., "HardwareC: A Language for Hardware Design", Stanford University Technical Report CSLTR -90-419 (1990), Version 2.0.

No context found.

D. Ku and G.D. Micheli. HardwareC - a language for hardware design (version 2.0). Technical Report CSL-TR-90-419, Stanford University, April 1990.

No context found.

Ku, D.C. and De Micheli, D.: HardwareC -- A Language for Hardware Design. Stanford University, Technical Report CSL-TR-90-419, 1988.

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Ku, D., and De Micheli, G. HardwareC---A Language for Hardware Design (version 2.0). Tech. Rep. CSL-TR90 -419, Stanford University, 1990.

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David Ku and Giovanni De Micheli. HardwareC - A language for hardware design, version 2.0. Technical report, Stanford University, 1990.

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D. Ku, G. De Micheli. "HardwareC -- A Language for Hardware Design, Version

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D. Ku and G. De Micheli, HardwareC---A Language for Hardware Design (Version 2.0), Tech. Report CSL-TR-90-419, Stanford Univ., Stanford, Calif., 1990.

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Ku 90 D. Ku and G. De Micheli, "HardwareC - A Language for Hardware Design," Tech. Report CSL-TR-90-419, Stanford University, Stanford CA, 1990.

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