R. Gupta and G. DeMicheli, "Hardware-software cosynthesis for digital systems," IEEE Design Test Comput. Mag., pp. 29--41, Oct. 1993.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....We assume only one level of memory hierarchy and the only thing we can do is to refuse a client if he requests more memory than available. Today much effort has been put into making hardware synthesis from C possible[6] Solutions such as Ocapi, SystemC, HardwareC have been presented[7] 8][9]. Common for all of these systems is the desire to bring the hardware design process to a higher level of abstraction. C use in hardware design is still primitive since it is on RTL The full power of high level design language can be realised only when higher level constructs and memory ....

9. R.K.Gupta, De-Micheli-G, "Hardware-software cosynthesis for digital systems", 1EEE design and Test of Computers, vol. 10, no.3; Sept. 1993;

....implementation model, which may be viewed as co simulation at a high abstraction level. In the following some hardware software co design methodologies are discussed in more detail. For a more elaborate overview on the hardware software co design process see [30] or [79] Vulcan Vulcan [41] [40] has mainly been developed for co synthesis. The functionality is formulated in HardwareC, which is based on C and models a system as concurrent processes communicating with each other. The target architecture consists of a processor, a memory and a set of ASICs . Co synthesis starts with ....

R. K. Gupta and G. D. Micheli. Hardware-software cosynthesis for digital systems. IEEE Design & Test of Computers, 10(3):29--41, September 1993.

.... that allows a designer to manually or automatically partition an embedded system specification between different processors [49] Gupta and De Micheli developed an iterative improvement algorithm to partition real time embedded systems between a co processor and a general purpose processor [50]. Henkel and Ernst developed a dynamic granularity simulated annealing algorithm for hardwaresoftware partitioning [51] Kalavade and Lee designed a constructive algorithm that partitions a system specification between hardware and software by traversing a list of tasks [52] It dynamically ....

R. K. Gupta and G. De Micheli, "Hardware-software cosynthesis for digital systems, " IEEE Design and Test of Computers, vol. 10, pp. 29--41, Sept. 1993.

.... from a behavioral to a structural representation and ends up to a physical representation, enriched with implementation details along each step [3] A lot of algorithms exist for the efficient partitioning of a system (Greedy, Hillclimbing, A binary constraint search algorithm [3] In [2] and [6], hardware software partitioning systems are described along with the algorithms used and co simulation techniques. In practice, the analysis of trade offs for partitioning a system is most often an informal process based on the experience of the system architect [13] The methodology adopted in ....

R. Gupta and G. DeMicheli. Hardware-software cosynthesis for digital systems. IEEE Design & Test of Computers, pages 29--41, October 1993.

....6 we present the conclusions. 2. Previous Related Work There are a great number of approaches to HW SW codesign of embedded systems, which use different techniques for partitioning and scheduling. Earlier approaches to HW SW partitioning model the system based on a template of a CPU and an ASIC [8, 11]. Moreover, several types of algorithms (constructive or iterative) have been used [21] In the other hand, configuration prefetching techniques can be used for reconfiguration latency minimization. They are based on the idea of loading the next reconfiguration context before it is required, ....

R. Gupta, G. De Micheli, "Hardware-Software cosynthesis for Digital Systems". IEEE Design and Test of Computers, vol. 10, no. 3, pp 29-41, Sept. 1993.

....as much as possible of the highest priority tasks as possible, so that they do not have to be brought into the cache again. 1.1 Related Work Most of the early work in Hardware Software Co Synthesis was constrained to a single processor and ASIC. Work by Henkel et. al [2, 3] Gupta et. al [4, 5] and Parameswaran et al. [6, 7] Prakash and Parker published a mixed integer Linear Programming (MILP) approach [8] to synthesize multiple processor architectures for a specific application. This work was enhanced by the authors in [9] to include memory costs into the final implementation. Due to ....

R. K. Gupta and M.-G. De, "Hardware-software cosynthesis for digital systems," IEEE Design & Test of Computers, vol. 10, pp. 2941 Phys Sci & Engin Journal holding 21(1984)- 1912(1995);1913(1996)-, 1993.

....through 0, 1, 2, and n CPUs for software implementation. 3.2.2Binary Search Copartitioning (BSC) Level Thisbinary search copartitioning (BSC) level forms the core part of hardware software copartitioning. We do not start from either of the two extreme solutions found in existing methods [4], 15] all hardware and all software. Rather we start somewhere in between and then based on two heuristic assumptions, we start moving towards theheuristically optimal feasible solution. The two heuristic assumptions are as follows. 1) First assumption is that hardware implementations alway s ....

R.K. Gupta and G. De Micheli,"Hardw are-softw are cosynthesis for digital systems," IEEE Design and Test of Computers, vol.10, no.3, pp.29--41, Sept. 1993.

....process vanishes. Originally intended for software design, neither C nor C has the basic support required for accurately dealing with the hardware parts of a SoC design. There are two approaches for building this type of hardware support. The first approach relies on syntax extension [2,7,9,12,16] and requires the development of separate compilers, simulators, and synthesis tools to manipulate the new syntax. In this paper we look at the second approach which relies on class libraries to model the hardware aspects of the SoC design and can only be used with languages that are extensible ....

R. Gupta and G. De Micheli, "Hardware/Software Cosynthesis of Digital Systems", IEEE Design and Test of Computers, pp. 29- 41, September 1993.

....for low power embedded systems should be performed in tight integration with high level synthesis (HLS) under the guidance of an accurate timing and power evaluation (estimation) mechanism. This is the topic of this paper. Many of the existing hardware software co synthesis methodologies [1] [8] [18] contemplate an abstract modeling of hardware by considering generic properties such as its capacity to concurrently execute operations and to be shared by similar operations. As a result, co synthesis and HLS are successive and independent activities. This is a valid assumption if objective ....

....execution. The link between co synthesis and HLS, however, has to be much stronger if fine performance trade offs between conflicting performance constraints i.e. latency and power are examined. Also, system functionality is traditionally described as a task graph with data dependencies, only [4] [8] [10] 18] This implies that co synthesis does not address any conditional behavior expressed with control dependencies. Nevertheless, handling control dependencies enables more precise performance estimations, more effective design decisions i.e. scheduling and ultimately, better quality ....

R. Gupta et al, "Hardware-Software Cosynthesis for Digital Systems", IEEE Design & Test of Computers, September 1992, pp.29-40.

....areas of hardware software co design and reconfigurable computing. Earlier work in hardware software co design mainly focused on hardware software partitioning. Most of the partitioning algorithms model the system based on an architectural template of a CPU (software) and an ASIC (hardware) 4] [5][7] 11] Recent work in co synthesis has used a more generalized model consisting of heterogeneous multiprocessors with various communication topologies [2] 9] 10] Although some of the above techniques use highly abstract architecture models that might be retargetable to reconfigurable ....

R. Gupta and G. De Micheli, "Hardware-software cosynthesis for digital systems," IEEE Design and Test of Computers, vol.10, no.3, pp.29-41, Sept. 1993.

....SOC This approach to system synthesis diverges from the traditional cosynthesis methods. Usually, a system is described using a behavioral description, then a circuit is synthesized using elements from a library of predesigned components, and software is compiled to run on the generated hardware [8]. In our approach, the application is described by writing software for a complete processor core. Then, during optimization prior to synthesis, the subset of the entire core needed to run the application software is extracted and synthesized, thus leading to application specific synthesis. A ....

R.K. Gupta, G. De Micheli. "Hardware-Software Cosynthesis for Digital Systems". IEEE Design & Test of Computers, volume 10, number 4, September 1993, pp. 2940

....behind this research is to allow the design and implementation of modern systems including both hardware and software. Several projects currently in progress (SpecSyn at Irvine [7] CODES at Siemens [4] SDW at Italtel [1] Thomas approach at CMU [2] Gupta and De Micheli approach at Stanford [8], Wolf approach at Princeton University [13] Chinook at the university of Washington [6] Ptolemy at Berkeley [10] are trying to integrate both hardware and software in the same design process. The long term objective of this research work is to develop methods and tools for hardware software ....

R.Gupta, G. DeMicheli, "Hardware-Software Cosynthesis for Digital Systems", IEEE Design and Test of Computers, pp. 29-41, September 1993.

....07558038 and 07680353 from the Ministry of Education, Science and Culture, Japan. or SW. In order to produce an efficient result in reasonable design time, an efficient HW SW codesign partitioning method should be used. Many HW SW partitioning methods have been proposed. Gupta and De Micheli [2] introduced a method that moves operations from HW to SW to meet performance constraint at minimal cost. Ernst, et al. 3] take the opposite approach moving time critical operations from SW to HW. Woo, et al. 4] introduced a codesign method that divides the operations into HW,SW and codesign ....

R. Gupta and G. De Micheli: "Hardware-Software Cosynthesis for Digital Systems," IEEE Design & Test, pp. 29 -- 41, Sep. 1993.

....system implementation moving pieces of software toward the hardware domain and, viceversa, strategies aiming at obtaining the minimum cost by replacing pieces of hardware with software code. Two pioneer researches, representing this duality of goals, are COSYMA [Ben93] and VULCAN II [Gup92] [Gup93]. The first assumes as input of the co design flow a textual specification written in the C x language, a C extension supporting task level concurrence and timing constraints. Such a specification is translated into an internal representation (Extended Syntax Graph) on which preliminary ....

R.K.Gupta, G.De Micheli, Hardware-Software Cosynthesis for Digital Systems, IEEE Design&Test, September 1993.

....hard realtime rate monotonic scheduling based ASIC design allows several tasks to share the same hardware during their execution. Hardware software codesign has received a great deal of attention recently [Wol94] The most relevant system research subdomain is hardware software partitioning [Bar94, Ern93, Gup93, Vah92]. These algorithms try to identify parts of computations which should be implemented on programmable and ASIC platform so that an overall optimization function is maximized. However, they do not address use and influence of hard real time operating scheduling constrains and operating systems ....

R. K. Gupta and G. De Micheli, "Hardware-software cosynthesis for digital systems," IEEE Design & Test of Computers, 10(3), pp. 29-41, 1993.

....successive realizations from the same specification. Thus, different explorations of an hardware software design space defined by specifications and constraints are needed to exhibit successive solutions. Recent works propose codesign or cosynthesis methodologies.For example, approaches in [10], 8] deal with a C style specification augmented with timing constraints, task concept and communication facilities. In these approaches partitioning the specification is based on cost functions that estimate software, hardware and communication character Proceedings Int. Workshop on ....

GUPTA R.K., DE MICHELI G. Hardware-Software Cosynthesis for Digital Systems. IEEE Journal Design and Test of Computers. 29-41, september, 1993.

....developed on the basis of performance and cost estimations of implementations of tasks on both the software and hardware units. Obviously, increasing accuracy of estimates may lead to more efficient HW SW system partitioning. Several techniques for partitioning a specification have been proposed, [7], 4] 9] for example. In [7] a partitioning algorithm is proposed that considers an initial hardware implementation and iteratively re assigns operations to the software unit if the cost is lessen at each step. In [4] the algorithm operates in opposite way: from an initial solution where ....

....and cost estimations of implementations of tasks on both the software and hardware units. Obviously, increasing accuracy of estimates may lead to more efficient HW SW system partitioning. Several techniques for partitioning a specification have been proposed, 7] 4] 9] for example. In [7], a partitioning algorithm is proposed that considers an initial hardware implementation and iteratively re assigns operations to the software unit if the cost is lessen at each step. In [4] the algorithm operates in opposite way: from an initial solution where operations are all assigned to the ....

GUPTA R.K., DE MICHELI G., Hardware-Software Cosynthesis for Digital Systems. IEEE Journal Design and Test of Computers. 29-41, september, 1993.

....logic formulas handled by the Xtl model checker included in the Cadp toolbox. Keywords. Veri cation, Model Checking, LOTOS, Communicating Finite State Machine, Codesign. 1 Introduction For the design of complex systems the designers use ever more CAD tools working at the system level [GM93,Wol94,GV95,ELLSV97] Such tools o er generally the following capabilities : formal or abstract speci cation of the system, veri cation at the speci cation level, architecture exploration linked with performance analysis, automatic synthesis of behaviour and communication, automatic ....

R.K. Gupta and G. de Micheli. Hardware-Software Cosynthesis for Digital Systems. IEEE Design & Test of Computers, 10(3):29-41, September 1993.

.... The e#cacy of some low power high level design techniques has been demonstrated on several image and video processing circuits [Cat98, Nac98] and speech encoders [Hen97] As embedded applications have become more sophisticated, hardware software co design has become increasingly important [Gup93, Hen95] Key optimization problems in hardware software co design have been identified as system component allocation, functional partitioning, quality metrics estimation, model refinement [Wil94, Gon97] memory allocation using memory reuse for arrays and storage order [DeG97] The increased ....

R.K. Gupta and G. De Micheli. Hardware-software cosynthesis for digital systems. IEEE Design and Test of Computers, vol.10, (no.7), pp. 29-41, 1993.

....through several examples.Secple 6 LEE et al. HARDWARE SOF 665 MULTI LEVEL PARTITIONING 615 cDc:D:D theartic3 with some future work. 2. PreviousWork Hardware software partitioningtec hniques for the 1CPU 1 ASIC topology have been studied by many researc hers. Gupta and DeMic heli [2] [3] at Stanford University developed the VULCAN cLCAN thesis system, based on the Olympus high level synthesis [4] COSYMA (COSYnthesis of eMbeddedArc hitec tures) developed by Ernst et al. 5] 6] at Tec hnic2 University of Braunsc hweig, is an experimental cl synthesis system for ....

R.K. Gupta and G. De Micheli, "Hardware-software cosynthesis for digital systems," IEEE Design and Test of Computers, vol.10, no.3, pp.29--41, Sept. 1993.

....a larger range of real time systems using Signal and second, the integration of Signal and other languages like Alpha in a co design framework. The term co design has been used to denote the specification, validation and implementation of systems consisting of both hardware and software components [22, 23]. Since Signal and Alpha have complementary properties, they can be used in a hw sw codesign framework in which the Alpha language would specify and synthesize the hardware parts of a system and Signal will describe the software. The Signal Alpha cooperation will thus respond to some of the ....

....be used in a hw sw codesign framework in which the Alpha language would specify and synthesize the hardware parts of a system and Signal will describe the software. The Signal Alpha cooperation will thus respond to some of the problems existing in co design, like system specification and synthesis[16, 22]. ....

Gupta, R. K., de Micheli, G.: Hardware-Software Cosynthesis for Digital Systems. IEEE Design & Test of Computers (September 1993) 29--41

....codesign is partitioning. Indeed, we must identify which part of a system should be implemented in software and which part in hardware. At this time, there are only a few approaches dealing with an automatic hardware software partitioning. The Standford approach is hardware oriented [12]. The input language is Hardware C, a subset of C defined for hardware description. The initial implementation of a system is hardware based, except program constructs with unbounded delays. Then, the design system, Vulcan, tries to gradually move hardware functions to software, checking timing ....

....10 shows the communication between the different tools and the interface with others languages like C, Fortran, etc. The third point presents the different techniques now used in Hardware Software codesign [18, 13] Three main approaches are emerging: software oriented [9] hardware oriented [12], and a theoretical approach [18] The next step is to apply these different techniques on benchmarks like FIR16, MICDA, in order to give quantitatives results. 16 VHDL Alpha Subset of GC OSYS, GAUT VHDL C, Fortran Lustre Signal Figure 10: Communication between tools ....

R. Gupta and G. De Micheli. Hardware-software cosynthesis for digital systems. Computer, 29--41, September 1993.

....for each component. Incorporating such knowledge, especially that required for estimation, is very difficult, which is the reason that current tools only support a subset of possible allocations, such as a particular interconnection of a standard processor, memory, bus and custom processor [12] [13]. While SpecSyn permits a variety of allocations, its estimation models and heuristics must continually be improved to better apply to each. Each component is characterized in a library by its constraints, and by a technology file. For example, a custom processor might be characterized by the ....

....of functional partitioning over the current practice of structural partitioning [22] Hardware software partitioning techniques form the second functional partitioning category. These techniques focus on partitioning functionality among a hardware software architecture. The techniques in [12] [13], 23] and [24] 27] partition at the statement, statement sequence and subroutine task levels, respectively. In SpecSyn, both the hardware and hardware software partitioning techniques are supported, since one can allocate any combination of hardware and software components and assign pieces ....

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R. Gupta and G. DeMicheli, "Hardware-software cosynthesis for digital systems," IEEE Design Test Comput., pp. 29--41, Oct. 1993.

....electronic fuel injection, portable CD players or palm top computers. Stringent processing and reliability requirements imposed on these complex systems as well as the need for low cost and little time to market make a revision of the traditional design methods necessary. A number of authors [2,3,7,8,13] have been suggesting various approaches to address these issues using hardware software codesign. We have been proposing a high level system design approach called model based codesign that relies heavily on simulation modeling techniques to explore the feasibility of virtual prototypes [1,12] ....

R.K. Gupta and G. De Micheli, "Hardware-Software Cosynthesis for Digital Systems", IEEE Design and Test of Computers, 10(3), pp. 29-41, 1993.

....(For more information on how to se (a) Bus A C SYSTEM B CTRL B NEW PROC ASIC (b) SYSTEM A C B x MEM (x) Figure 1: An example of model refinement: a) an input specification, b) the refined specification. lect a good allocation and partition please refer to related work in [1, 2, 3]) After partitioning, the model refinement task is required to transform the original specification into a refined specification to reflect the allocation and partitioning decisions. For example, the refined specification (Figure 1(b) shows that one processor and one ASIC are used for the ....

....verification, behavioral synthesis or software compilation tasks that may follow hardware software codesign. ED TC 96 0 89791 821 96 5.00 1996 IEEE Previous work in hardware software codesign has addressed many issues. Functional partitioning among system components has been discussed in [1,2,3]. Simulation environments have been developed to encourage early functional verification [4, 5] and various techniques [6, 7] have been proposed to interface hardware and software components. Our work is closely related to hardware software interfacing. However, instead of focusing on the ....

R. Gupta and G. DeMicheli, "Hardware-software cosynthesis for digital systems," in IEEE Design & Test of Computers, pp. 29--41, October 1993.

....safety, select a specific application, i.e. an autonomous, intelligent cruise controller, and propose model based techniques for a realization of such a device. 2. Model based codesign A multitude of codesign techniques and methodologies are employed in academic and commercial environments [7,8,9,12,18,19]. A common trend appears to be emerging in which a clear shift in design and development paradigms is occurring. Initial approaches would foster immediate partitioning into hardware (HW) and software (SW) components, pursue HW and SW development threads in isolation from each other, and often ....

R.K. Gupta and G. De Micheli, Hardware-Software Cosynthesis for Digital Systems, IEEE Design and Test of Computers, 10(3), 29-41, 1993.

....containing programmable processors that are employed for applications other than generalpurpose computing are called embedded systems. B. Hardware Software Co Design Rather than designing the software and hardware componentsof an embeddedsystem separately, hardware softwareco design (e.g. [1]) is more cost effective and results in a shorter time to market. In this design methodology, designers partition the system functionality into hardware and software. Additionally, a target processor is chosen from existing processor designs, or an ASIP (Application Specific Instruction Set ....

....The last set of brackets in each operation contains timing information. Note that if the ADC operation were to assign values to the DBM bitfields, then a bitfield conflict with DBM operations would result, and this should be reflected in the Constraints section. Section Constraints ( REP ) [1] DO , This constraint denotes that any DO instruction is illegal when fetched as the next instruction after a REP instruction. The [1] indicates a time shift of one instruction fetch for the DO instruction. See [11] for a more extensive example. V. AUTOMATIC ASSEMBLER GENERATOR We required ....

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R. K. Gupta and G. De Micheli. Hardware--Software Cosynthesis for Digital Systems. IEEE Design & Test of Computers, pages 29--41, September 1993.

....to the evaluation of a cost function = that takes the above mentioned parameters into consideration. A practical approach is to allocate all blocks in hardware and then to move to software those tasks whose = remains within a given value (usually called hardware oriented approach, see for example [Gupta and Micheli 1993]) Of course, we can also do the opposite, as in [Ernst and J. 1993b] In order to evaluate = correctly, we need to determine the cost of each task. Some of the approaches proposed in literature are based on cosimulation [Wilson 1994] Rowson 1994] some are based on soft computing techniques ....

Gupta, R. K. and Micheli, G. D. 1993. Hardware-Software cosynthesis for digital systems. IEEE Design and Test Computer.

....information supporting the partitioning scheme. The methodology has been weakened by the lack of effective partitioning strategies. It instead provides the effective and rapid system simulation. 2. Graph Based Methodology In contrast with paper No. 1, Rajesh K. Gupta et al. paper No. 3)[4] demonstrates the feasibility of synthesising hardware software systems by using timing constraints to delegate tasks between hardware and software so that performance requirements can be met. The methodology seeks automatic synthesis of the system from a unified specification that is written by ....

....of California, Berkeley ) A Hardware Software Codesign Methodology for DSP Application[3] A codesign methodology applicable to digital signal processing and communications system 3 Rajesh K. Gupta et al. Stanford University ) Hardware Software Cosynthesis for Digital Systems[4] A synthesis oriented approach to digital circuit design 4 Sanjaya Kumar et al. University of Virginia ) A Framework for Hardware Software Codesign [5] An integrated hardware software model, System cosimulation and evaluation 5 Nam S. Woo et al. AT T Bell Labs Princeton ....

Ralesh K. Gupta and Giovanni De Micheli, "Hardware-Software Cosynthesis for Digital Systems", in IEEE Design & Test of Computers, Vol. 10, No. 3, September 1993, pp. 29-41.

....[10] we ensure the deterministic behavior of a component. For a more extensive comparison of synchronous languages the reader may refer to [9] Hardware software partitioning issues have not been considered so far, nevertheless our approach is also related to software hardware co design [20] environments for embedded system such as Polis [2] VULCAN [21] COSYMA [7] Chinook [5] etc. The closest to our approach is Polis. Others systems are either based on variations of the C language or on HDL language. Compared Irisa A Synchronous Approach for Hardware Design 31 to Polis, rather ....

R.K.Gupta and Giovanni De Micheli. Hardware-Software Cosynthesis for Digital Systems. IEEE Design & Test of Computers, pages 29--41, September 1993.

....and therefore fault tolerance, have also become important concerns. Thus, there is also a need to incorporate fault tolerance features during co synthesis. Researchers have primarily focused their interest in last several years on hardware software co synthesis of one CPU one ASIC architectures [3] [9] where attempts have been made to move operations from hardware to software or vice versa to minimize cost and meet deadlines. In the area of distributed system co synthesis, the target architecture can employ multiple CPUs, ASICs, and field programmable gate arrays (FPGAs) 12] Two distinct ....

R. K. Gupta, Hardware-software Cosynthesis of Digital Systems, Ph.D. thesis, Stanford University, 1994.

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R.K. Gupta and G. De Micheli. Hardware-software cosynthesis for digital systems. IEEE D&T, Sept. 1993.

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R.K. Gupta and G. De Micheli. Hardware-software cosynthesis for digital systems. IEEE Design and Test of Computers, September 1993.

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R. K. Gupta and G. D. Micheli, "Hardware-software cosynthesis for digital systems," IEEE Des. Test Comput., pp. 29--41, Sept. 1993.

....In Section 5, we describe the changes required in the software to use the hardware interface and explain three hardware software interfacing schemes. In Section 6, we describe our MPEG 1 case study and then, conclude the report with a discussion. 2 Related Work Hardware software partitioning [2, 3] and high level synthesis [4, 5] have received significant attention over the past decade. Interface synthesis techniques have focused on various issues like optimizing the use of external IO pins of micro controllers and minimizing glue logic [6] However, the use of memory mapping for interface ....

....has not been considered. Furthermore, hardware software co design methodologies that synthesize the hardware component as an ASIC, pay little attention towards optimizing the memory mapping since the amount of logic that can be mapped to an ASIC is less severely constrained than that for FPGAs [2, 7, 8]. Most previous work on memory mapping and allocation of multiport memories has been done in the context of data path synthesis and has focused on purely data flow designs (no control constructs) 9, 10, 11] These algorithms do not deal with unknown data access patterns because no control flow ....

R.K. Gupta and G. De Micheli. Hardware-software cosynthesis for digital systems. IEEE Design and Test of Computers, September 1993.

....memory space, whereas the application specific hardware components essentially operate as data driven reactive computational elements. Because of this difference in the hardware and software components, the problem of system synthesis is formulated as a hardware software co synthesis problem[11]. 2 An Overview of our Co synthesis Approach Figure 1 illustrates the overall approach to synthesis of systems containing both hardware and software components. We model system behavior using a hardware description language, HardwareC [12] language that has a C like syntax and supports timing ....

....extends and builds upon techniques for synthesis of hardware. Further, the particular choice of HardwareC is immaterial for the co synthesis formulation, and one could use other HDLs such as Verilog or VHDL. The input HDL description is compiled into a system graph model based on data flow graphs [11, 13]. The system graph model consists of vertices representing operations, and edges which represent serialization among operations. Overall the system graph model is composed of concurrent data flow sections which are ordered by the system control flow. Associated with input output statements, the ....

R. K. Gupta and G. D. Micheli, "Hardware-Software Cosynthesis for Digital Systems," IEEE Design & Test of Computers, pp. 29-41, Sept. 1993.

....is described as a software program in an extension of the C programming language. The system model is compiled into a control dataflow graph and a partitioning algorithm identifies the computational bottlenecks which are implemented as application specific hardware. The Vulcan synthesis tool suite [3, 4, 5] uses instead a hardware model of the system (in the HardwareC language) and attempts to reduce the cost of a full hardware implementation by transferring non critical operations to routines executing on a standard processor or processor core. The system model is again compiled into a ....

....and executed on the standard processor and (ii) the specification of the remaining hardware circuits, that can be synthesized as a netlist of logic gates. Hardware software synchronization units for interfacing the processor to the application specific logic are also automatically generated [3, 5, 6]. Both Cosyma and Vulcan partition the system specification with a fine granularity, i.e. partition blocks are sets of operations. Conversely, the Co SAW tool suite [7] partitions systems with a coarse granularity, i.e. blocks correspond to processes. Whereas some optimality is lost in using a ....

R. Gupta and G. De Micheli, "Hardware-Software Cosynthesis for Digital Systems," IEEE Design & Test of Computers, pp. 29-41, September 1993.

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R. Gupta and G. DeMicheli, "Hardware-software cosynthesis for digital systems," IEEE Design Test Comput. Mag., pp. 29--41, Oct. 1993.

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R. Gupta, G. De Micheli. Hardware-Software Cosynthesis for Digital Systems. IEEE Design & Test of Computers, pages 29-41, September 1993.

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R. K. Gupta and G. De Micheli, "Hardware-Software Cosynthesis for Digital Systems", IEEE Des. & Test Comput., vol. 10, no. 3, pp. 29-41, Sept. 1993.

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R. Gupta, G. De Micheli. Hardware-Software Cosynthesis for Digital Systems. IEEE Design & Test of Computers, pages 29-41, September 1993.

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R.K. Gupta, and G. de Michelli, Hardware/Software Cosynthesis for Digital Systems, IEEE Design & Test of Computers, Vol. 10 No. 4, pp. 29-41, December 1993.

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R.Gupta, G.De Micheli, "Hardware-software cosynthesis for digital systems ", IEEE Design and Test of Computers, Vol.10, No.3, pp.29-41, Sep. 1993.

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R.Gupta, G.De Micheli, "Hardware-software cosynthesis for digital systems", IEEE Design and Test of Computers, Vol.10, No.3, pp.2941, Sep. 1993.

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R. Gupta, G. De Micheli. Hardware-Software Cosynthesis for Digital Systems. IEEE Design & Test of Computers, pages 29-41, September 1993.

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R.K. Gupta and G. De Micheli, "Hardware-software cosynthesis for digital systems," IEEE Design & Test of Computers, vol. 10, no. 3, pp. 29-40, September 1993.

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Gupta, R. and De Micheli, G. Hardware-software cosynthesis for digital systems. IEEE Design & Test of Computers 10, 3, (Sept 1993), 29-41.

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R.K. Gupta and G. De Micheli, "Hardware-software cosynthesis for digital systems," IEEE Design & Test of Computers, vol. 10, no. 3, pp. 29-40, September 1993.

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R.K. Gupta, G. DeMicheli, Hardware-Software Cosynthesis for Digital Systems, IEEE Design & Test of Computers, pp29-40, Sept. 1993

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R. K. Gupta. Hardware-software cosynthesis for digital systems. IEEE Design and Test of Computers, pages 29--41, Spetember 1993.

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