R. Gupta and G. DeMicheli, "Hardware-software cosynthesis for digital systems," IEEE Design Test Comput. Mag., pp. 29--41, Oct. 1993. Home/Search Document Details and Download
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An Efficient Dynamic Memory Manager for Embedded Systems - Millberg (Correct)
....We assume only one level of memory hierarchy and the only thing we can do is to refuse a client if he requests more memory than available. Today much effort has been put into making hardware synthesis from C possible[6] Solutions such as Ocapi, SystemC, HardwareC have been presented[7] 8][9]. Common for all of these systems is the desire to bring the hardware design process to a higher level of abstraction. C use in hardware design is still primitive since it is on RTL The full power of high level design language can be realised only when higher level constructs and memory ....
9. R.K.Gupta, De-Micheli-G, "Hardware-software cosynthesis for digital systems", 1EEE design and Test of Computers, vol. 10, no.3; Sept. 1993;
System Modeling and Design Refinement in ForSyDe - Sander (2003) (Correct)
....implementation model, which may be viewed as co simulation at a high abstraction level. In the following some hardware software co design methodologies are discussed in more detail. For a more elaborate overview on the hardware software co design process see [30] or [79] Vulcan Vulcan [41] [40] has mainly been developed for co synthesis. The functionality is formulated in HardwareC, which is based on C and models a system as concurrent processes communicating with each other. The target architecture consists of a processor, a memory and a set of ASICs . Co synthesis starts with ....
R. K. Gupta and G. D. Micheli. Hardware-software cosynthesis for digital systems. IEEE Design & Test of Computers, 10(3):29--41, September 1993.
Multiobjective Synthesis of Low-Power Real-Time Distributed.. - Dick (2002) (1 citation) (Correct)
.... that allows a designer to manually or automatically partition an embedded system specification between different processors [49] Gupta and De Micheli developed an iterative improvement algorithm to partition real time embedded systems between a co processor and a general purpose processor [50]. Henkel and Ernst developed a dynamic granularity simulated annealing algorithm for hardwaresoftware partitioning [51] Kalavade and Lee designed a constructive algorithm that partitions a system specification between hardware and software by traversing a list of tasks [52] It dynamically ....
R. K. Gupta and G. De Micheli, "Hardware-software cosynthesis for digital systems, " IEEE Design and Test of Computers, vol. 10, pp. 29--41, Sept. 1993.
Verification of a complex SoC; the PRO³ case-study - Andritsopoulos.. (Correct)
.... from a behavioral to a structural representation and ends up to a physical representation, enriched with implementation details along each step [3] A lot of algorithms exist for the efficient partitioning of a system (Greedy, Hillclimbing, A binary constraint search algorithm [3] In [2] and [6], hardware software partitioning systems are described along with the algorithms used and co simulation techniques. In practice, the analysis of trade offs for partitioning a system is most often an informal process based on the experience of the system architect [13] The methodology adopted in ....
R. Gupta and G. DeMicheli. Hardware-software cosynthesis for digital systems. IEEE Design & Test of Computers, pages 29--41, October 1993.
A HW/SW Partitioning Algorithm for Dynamically Reconfigurable .. - Noguera, Badia (2001) (1 citation) (Correct)
....6 we present the conclusions. 2. Previous Related Work There are a great number of approaches to HW SW codesign of embedded systems, which use different techniques for partitioning and scheduling. Earlier approaches to HW SW partitioning model the system based on a template of a CPU and an ASIC [8, 11]. Moreover, several types of algorithms (constructive or iterative) have been used [21] In the other hand, configuration prefetching techniques can be used for reconfiguration latency minimization. They are based on the idea of loading the next reconfiguration context before it is required, ....
R. Gupta, G. De Micheli, "Hardware-Software cosynthesis for Digital Systems". IEEE Design and Test of Computers, vol. 10, no. 3, pp 29-41, Sept. 1993.
Code placement in Hardware Software Co synthesis to improve.. - Parameswaran (2001) (Correct)
....as much as possible of the highest priority tasks as possible, so that they do not have to be brought into the cache again. 1.1 Related Work Most of the early work in Hardware Software Co Synthesis was constrained to a single processor and ASIC. Work by Henkel et. al [2, 3] Gupta et. al [4, 5] and Parameswaran et al. [6, 7] Prakash and Parker published a mixed integer Linear Programming (MILP) approach [8] to synthesize multiple processor architectures for a specific application. This work was enhanced by the authors in [9] to include memory costs into the final implementation. Due to ....
R. K. Gupta and M.-G. De, "Hardware-software cosynthesis for digital systems," IEEE Design & Test of Computers, vol. 10, pp. 2941 Phys Sci & Engin Journal holding 21(1984)- 1912(1995);1913(1996)-, 1993.
Unknown - Desc Hardware-Software Codesign (Correct)
....through 0, 1, 2, and n CPUs for software implementation. 3.2.2Binary Search Copartitioning (BSC) Level Thisbinary search copartitioning (BSC) level forms the core part of hardware software copartitioning. We do not start from either of the two extreme solutions found in existing methods [4], 15] all hardware and all software. Rather we start somewhere in between and then based on two heuristic assumptions, we start moving towards theheuristically optimal feasible solution. The two heuristic assumptions are as follows. 1) First assumption is that hardware implementations alway s ....
R.K. Gupta and G. De Micheli,"Hardw are-softw are cosynthesis for digital systems," IEEE Design and Test of Computers, vol.10, no.3, pp.29--41, Sept. 1993.
System Level Design Using C++ - Verkest, Kunkel, Schirrmeister (2000) (Correct)
....process vanishes. Originally intended for software design, neither C nor C has the basic support required for accurately dealing with the hardware parts of a SoC design. There are two approaches for building this type of hardware support. The first approach relies on syntax extension [2,7,9,12,16] and requires the development of separate compilers, simulators, and synthesis tools to manipulate the new syntax. In this paper we look at the second approach which relies on class libraries to model the hardware aspects of the SoC design and can only be used with languages that are extensible ....
R. Gupta and G. De Micheli, "Hardware/Software Cosynthesis of Digital Systems", IEEE Design and Test of Computers, pp. 29- 41, September 1993.
Integrated Hardware-Software Co-Synthesis and High-Level.. - Doboli (2001) (Correct)
....for low power embedded systems should be performed in tight integration with high level synthesis (HLS) under the guidance of an accurate timing and power evaluation (estimation) mechanism. This is the topic of this paper. Many of the existing hardware software co synthesis methodologies [1] [8] [18] contemplate an abstract modeling of hardware by considering generic properties such as its capacity to concurrently execute operations and to be shared by similar operations. As a result, co synthesis and HLS are successive and independent activities. This is a valid assumption if objective ....
....execution. The link between co synthesis and HLS, however, has to be much stronger if fine performance trade offs between conflicting performance constraints i.e. latency and power are examined. Also, system functionality is traditionally described as a task graph with data dependencies, only [4] [8] [10] 18] This implies that co synthesis does not address any conditional behavior expressed with control dependencies. Nevertheless, handling control dependencies enables more precise performance estimations, more effective design decisions i.e. scheduling and ultimately, better quality ....
R. Gupta et al, "Hardware-Software Cosynthesis for Digital Systems", IEEE Design & Test of Computers, September 1992, pp.29-40.
Hardware-Software Co-Design of Embedded - Reconfigurable Architectures.. (2000) (Correct)
....areas of hardware software co design and reconfigurable computing. Earlier work in hardware software co design mainly focused on hardware software partitioning. Most of the partitioning algorithms model the system based on an architectural template of a CPU (software) and an ASIC (hardware) 4] [5][7] 11] Recent work in co synthesis has used a more generalized model consisting of heterogeneous multiprocessors with various communication topologies [2] 9] 10] Although some of the above techniques use highly abstract architecture models that might be retargetable to reconfigurable ....
R. Gupta and G. De Micheli, "Hardware-software cosynthesis for digital systems," IEEE Design and Test of Computers, vol.10, no.3, pp.29-41, Sept. 1993.
A Method To Derive Application-Specific Embedded - Processing Cores Olivier (2000) (Correct)
....SOC This approach to system synthesis diverges from the traditional cosynthesis methods. Usually, a system is described using a behavioral description, then a circuit is synthesized using elements from a library of predesigned components, and software is compiled to run on the generated hardware [8]. In our approach, the application is described by writing software for a complete processor core. Then, during optimization prior to synthesis, the subset of the entire core needed to run the application software is extracted and synthesized, thus leading to application specific synthesis. A ....
R.K. Gupta, G. De Micheli. "Hardware-Software Cosynthesis for Digital Systems". IEEE Design & Test of Computers, volume 10, number 4, September 1993, pp. 2940
Interface Synthesis using Memory Mapping for an FPGA Platform - Manev Luthra Sumit (2003) (2 citations) Self-citation (Gupta) (Correct)
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R.K. Gupta and G. De Micheli. Hardware-software cosynthesis for digital systems. IEEE D&T, Sept. 1993.
Hardware and Interface Synthesis of FPGA Blocks.. - Gupta, Luthra.. Self-citation (Gupta) (Correct)
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R.K. Gupta and G. De Micheli. Hardware-software cosynthesis for digital systems. IEEE Design and Test of Computers, September 1993.
Specification and Analysis of Timing Constraints for.. - Gupta, De Micheli (1997) (3 citations) Self-citation (Gupta) (Correct)
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R. K. Gupta and G. D. Micheli, "Hardware-software cosynthesis for digital systems," IEEE Des. Test Comput., pp. 29--41, Sept. 1993.
Interface Synthesis using Memory Mapping for an FPGA.. - Luthra, Gupta, Dutt.. (2003) (2 citations) Self-citation (Gupta) (Correct)
....In Section 5, we describe the changes required in the software to use the hardware interface and explain three hardware software interfacing schemes. In Section 6, we describe our MPEG 1 case study and then, conclude the report with a discussion. 2 Related Work Hardware software partitioning [2, 3] and high level synthesis [4, 5] have received significant attention over the past decade. Interface synthesis techniques have focused on various issues like optimizing the use of external IO pins of micro controllers and minimizing glue logic [6] However, the use of memory mapping for interface ....
....has not been considered. Furthermore, hardware software co design methodologies that synthesize the hardware component as an ASIC, pay little attention towards optimizing the memory mapping since the amount of logic that can be mapped to an ASIC is less severely constrained than that for FPGAs [2, 7, 8]. Most previous work on memory mapping and allocation of multiport memories has been done in the context of data path synthesis and has focused on purely data flow designs (no control constructs) 9, 10, 11] These algorithms do not deal with unknown data access patterns because no control flow ....
R.K. Gupta and G. De Micheli. Hardware-software cosynthesis for digital systems. IEEE Design and Test of Computers, September 1993.
Short Papers - Techniques For Minimizing (1999) (1 citation) (Correct)
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R. Gupta and G. DeMicheli, "Hardware-software cosynthesis for digital systems," IEEE Design Test Comput. Mag., pp. 29--41, Oct. 1993.
Dynamic Hardware/Software Partitioning: A First Approach - Greg Stitt Roman (2003) (2 citations) (Correct)
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R. Gupta, G. De Micheli. Hardware-Software Cosynthesis for Digital Systems. IEEE Design & Test of Computers, pages 29-41, September 1993.
Partitioning Framework for Less Restricted Partitioning Problems - Oh, Ha (Correct)
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R. K. Gupta and G. De Micheli, "Hardware-Software Cosynthesis for Digital Systems", IEEE Des. & Test Comput., vol. 10, no. 3, pp. 29-41, Sept. 1993.
Dynamic Hardware/Software Partitioning: A First Approach - Stitt, Lysecky, Vahid (2003) (2 citations) (Correct)
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R. Gupta, G. De Micheli. Hardware-Software Cosynthesis for Digital Systems. IEEE Design & Test of Computers, pages 29-41, September 1993.
Protocol Selection and Interface Generation for HW-SW.. - Daveau, Marchioro.. (1997) (14 citations) (Correct)
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R.K. Gupta, and G. de Michelli, Hardware/Software Cosynthesis for Digital Systems, IEEE Design & Test of Computers, Vol. 10 No. 4, pp. 29-41, December 1993.
Strategy For Power Efficient Design Of Parallel Systems - Danckaert, Masselos.. (Correct)
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R.Gupta, G.De Micheli, "Hardware-software cosynthesis for digital systems ", IEEE Design and Test of Computers, Vol.10, No.3, pp.29-41, Sep. 1993.
Strategy for Power Efficient Combined Task and.. - Danckaert.. (1999) (Correct)
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R.Gupta, G.De Micheli, "Hardware-software cosynthesis for digital systems", IEEE Design and Test of Computers, Vol.10, No.3, pp.2941, Sep. 1993.
Dynamic Hardware/Software Partitioning: A First Approach - Greg Stitt Roman (2003) (2 citations) (Correct)
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R. Gupta, G. De Micheli. Hardware-Software Cosynthesis for Digital Systems. IEEE Design & Test of Computers, pages 29-41, September 1993.
Fast Performance Prediction for Periodic Task Systems - Xiaobo Sharon Hu (Correct)
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R.K. Gupta and G. De Micheli, "Hardware-software cosynthesis for digital systems," IEEE Design & Test of Computers, vol. 10, no. 3, pp. 29-40, September 1993.
A Detailed Cost Model for Concurrent Use With.. - Ragan, Sandborn, Stoaks (2002) (Correct)
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Gupta, R. and De Micheli, G. Hardware-software cosynthesis for digital systems. IEEE Design & Test of Computers 10, 3, (Sept 1993), 29-41.
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