D.D. Gajski, N.D. Du , A. Wu, anda . Lin. High-level synthesis: introduction to chip and system design, Bos on : Kluwer Acadv ic Publishers, 1992. Home/Search Document Not in Database Summary Related Articles Check |
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High-Level Synthesis of Distributed Logic-Memory.. - Huang, Ravi, Raghunathan, .. (2002) (2 citations) (Correct)
....the quality of designs synthesized by HLS tools do not favorably compare against manual designs, given the wide range of advanced architectural tricks that experienced designers employ. While the basic concepts in HLS (e.g. scheduling and resource sharing techniques) have been well established [1], 2] there is a need to extend the capabilities of HLS by importing various advanced techniques employed in the context of custom high performance architectures. We explore one such technique in this work, namely the use of distributed logic memory architectures. Several important application ....
D. D. Gajski, N. D. Dutt, A. C-H Wu, and S. Y-L Lin, High-level Synthesis: Introduction to Chip and System Design, Kluwer Academic Publishers, Norwell, MA, 1992.
Automated Correctness Condition Generation for Formal.. - Mansouri, Vemuri (1999) (Correct)
....We report experimental results indicating the effectiveness of the proposed technique and summarize our ongoing work to further strengthen it. 1. Introduction High level synthesis (hls) systems generate register transfer level (rtl) designs from algorithmic behavioral specifications (Figure 1) [19, 15, 48, 8, 53, 26]. The rtl design consists of a data path and a controller. This paper is an extension to the work presented in the International Conference on Formal Methods in Computer Aided Design [29] Nov 1998. c fl 1999 Kluwer Academic Publishers. Printed in the Netherlands. The data path consists of ....
....if an operator is control dependent on a control operator then it is not scheduled until after the control operator is scheduled. Current scheduling algorithms in high level synthesis generally assume that control operators introduce sequential control flow points into the cdfg being scheduled [19, 15, 48, 8, 53, 26]. For example, 11 all operators inside a case statement are scheduled only after the deciding expression has been scheduled. All statements following the case statement are scheduled only after all the branches of the case statement are scheduled. All statements inside a while statement are ....
Gajski, D., N. Dutt, A. Wu, and S. Lin: 1992, `High-Level Synthesis, Introduction to Chip and System Design'. Kluwer Academic Publishers.
ProGram: A Grammar-Based Method for Specification and Hardware.. - Öberg (1999) (Correct)
....pp 75 78, Rochester, New York, Sept. 1994. 9] P. Ellervee, A. Jantsch, J. berg, A. Hemani, H. Tenhunen, Exploring ASIC Design Space At System Level with a Neural Network Estimator , In Proc. of 7th IEEE ASIC Conference and Exhibit (ASIC 94) pp 67 70, Rochester, New York, Sept. 1994. [10] A. Jantsch, P. Ellervee, J. berg, A. Hemani, H. Tenhunen, Hardware Software Partitioning and Minimizing Memory Interface Traffic , In Proc. of EURO DAC 94, pp 226 231, Grenoble, France, Sept. 1994. 11] P. Ellervee, J. berg, A. Jantsch, A. Hemani, Neural Network Based Estimator to Explore ....
....This process is iterated until an acceptable solution is found. Such a methodology is termed specify explore refine methodology [15] Design space exploration is a complex task in general, but can be more manageable in a specific application domain 1.4. High Level Synthesis High Level Synthesis [10, 11, 12] is the task of translating a description of a design at the algorithmic level and translate it into a Register Transfer (RT) level description or an RT level netlist. Since most of the tool designers had been working with implementing DSP algorithms before the research started with HLS in the ....
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D. Gajski, N. Dutt, A. Wu, S. Lin, "High-Level Synthesis - Introduction to Chip and System Design", Kluwer Academic Publishers, 1992.
Improving the Schedule Quality of Static-List.. - Govindarajan, Vemuri (2000) (Correct)
....that have a low complexity and yet produce good quality schedules. The Time Constrained Scheduling (TCS) problem minimizes the number of functional units required to schedule a particular Data Flow Graph (DFG) within a specified number of time steps. Over the past few years a number of techniques [1, 2] have been proposed to solve the TCS problem. Heuristic list scheduling algorithms have been widely used for their low complexity and good performance. The complexity of a dynamic list scheduling algorithm, such as the Force Directed Scheduling (FDS) is 2 , where is the time ....
....scheduling algorithms have been widely used for their low complexity and good performance. The complexity of a dynamic list scheduling algorithm, such as the Force Directed Scheduling (FDS) is 2 , where is the time constraint and is the number of operations. Static list scheduling [1, 2] algorithms are the least complex among the known class of scheduling techniques with a linear time complexity of . Typically, static list scheduling algorithms, in order to maintain low complexity, do not perform any look ahead like that of FDS. The drawback is that, static list ....
D. D. Gajski et.al. "High-Level Synthesis: Introduction to Chip and System Design". Kluwer Academic Publishers, 1992.
Data and Memory Optimization Techniques for Embedded.. - Panda, Catthoor, Dutt, .. (2001) (14 citations) Self-citation (Dutt) (Correct)
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GAJSKI, D., DUTT, N., LIN, S., AND WU, A. 1992. High Level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publishers, Hingham, MA.
Hardware and Interface Synthesis of FPGA Blocks.. - Gupta, Luthra.. Self-citation (Dutt) (Correct)
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D. D. Gajski, N. D. Dutt, A. C-H. Wu, and S. Y-L. Lin. High-Level Synthesis: Introduction to Chip and System Design. Kluwer Academic, 1992.
Dynamically Increasing the Scope of Code Motions during .. - Gupta, Dutt, Gupta.. (2003) Self-citation (Dutt) (Correct)
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Gajski, D.D., Dutt, N.D., Wu, A.C.-H., and Lin, S.Y.-L.: `High level synthesis: introduction to chip and system design' (Kluwer Academic, Boston, MA, 1992)
A Transformation for Integrating VHDL Behavioral Specificatio:n - And Self-citation (Gajski) (Correct)
....with Viewloglc Systems Inc. 293 Boston Post Road West, Marlboro, MA 01752. 1994 ACM 0 89791 685 9 94 0011 1. 50 552 for traditional sequential programming constructs, such as loops, variable assignments, and branches for which there are simple techniques to generate a control dataflow graph [2, 10, 11, 12, 13]. As a result, tools accept only extremely limited forms of waits and signals. For example, some tools restrict each process to a single read or write of a signM. Other tools treat signals as variables, which changes the functionality. Most do not differentiate properly between simple, bus, and ....
D. Gajski, N. Dutt, C. Wu, and Y. Lin, High-Level Synthesis: Introduction to Chip and System Design. Boston, Massachusetts: Kluwer Academic Publishers, 1991.
Channel Mapping in System Level Design - Cai, Gajski (2003) Self-citation (Gajski) (Correct)
....and their representing interconnection topology. The simplest topology is illustrated by Figure 5(b) In this topology, all the PEs are connected to a single system bus. To keep the smallest number of inserted transducers and localize the traffic, we adopt hierarchically clustering algorithm [4] to improve the simplest interconnection topology. The hierarchical clustering algorithm considers a set of objects and groups them according to some measure of closeness. The two closest objects are clustered first and considered to be a single object for future clustering. The clustering process ....
D. Gajski, N. Dutt, S. Lin, and A. Wu. High Level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publishers, 1992.
Scheduling RTL in design Methodology - Shin, Gajski (2002) Self-citation (Gajski) (Correct)
....methodology and the program flow of the proposed RTL refinement tool. Section 4 takes a closer look at the scheduling algorithm. Section 6 shows the experimental results. Section 7 concludes the report with a brief summary and future work. 2. Motivation Much research for High level synthesis [GDLW92] has been going on since 1980s. Currently, many commercial and academical high level synthesis tools exist in Electronic Design Automation market but the design community wouldn t integrate them into its design methodology and design flow due to the following reasons: # they can support only ....
D. Gajski, N. Dutt, S. Lin, and A. Wu. High Level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publishers, 1992. 11
Using Global Code Motions to Improve the Quality of .. - Gupta, Savoiu.. (2002) Self-citation (Dutt) (Correct)
.... binding methodology that binds operations to functional units and variables to registers, such that operations with the same inputs or outputs are bound to the same functional units and then, variables that are inputs or outputs to the same functional units, are mapped to the same registers [8]. In this way, the interconnect between functional units and registers is reduced. Although this idea of binding with the aim of minimizing interconnect is not new, the formulation that we use in our approach to solve this problem is new, along with its integration in a high level synthesis ....
....caused by code duplication during code motions. Bergamaschi [18] proposes the behavioral network graph to bridge the gap between high level and logic level synthesis and aid in estimating the effects of one on the other. Binding techniques for reducing interconnect have also been studied before [8, 19, 20]. Tseng et al. 21] use clique partitioning heuristics to find a clique cover for a module allocation graph. Paulin et al. 22] perform exhaustive weight directed clique partitioning of a register compatibility graph to find the solution with the lowest combined register and interconnect costs. ....
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D. D. Gajski, N. D. Dutt, A. C-H. Wu, and S. Y-L. Lin. High-Level Synthesis: Introduction to Chip and System Design. Kluwer Academic, 1992.
Variable Mapping Of System Level Design - Cai, Gajski (2002) Self-citation (Gajski) (Correct)
....time of variables. It computes the memory size by adding up the size of variables mapped to the memories. It uses integer linear program to produce the optimal mapping result. The register allocation and variable register binding problem has been discussed in the field of high level synthesis. [5] introduces some related algorithms including clique partitioning, left edge algorithm, and weighted bipartitematching algorithm. We notice that the difference between variable memory mapping problem in the system synthesis domain and variable register binding problem in the high level synthesis ....
D. Gajski, N. Dutt, S. Lin, and A. Wu. High Level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publishers, 1992.
Unknown - Synthesis-Ba Sed Softwa (Correct)
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D.D. Gajski, N.D. Du , A. Wu, anda . Lin. High-level synthesis: introduction to chip and system design, Bos on : Kluwer Acadv ic Publishers, 1992.
Increasing Hardware Efficiency with Multifunction Loop.. - Fan, Kudlur, Park, Mahlke (2006) (Correct)
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D. D. Gajski et al. High-level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publishers, 1992.
Behavioral Level Guidance Using Property-Based Design.. - Lisa Marie Guerra (1996) (1 citation) (Correct)
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D. Gajski, N. Dutt, A. Wu, and S. Lin, High-Level Synthesis: Introduction to Chip and System Design, Kluwer Academic Publishers, Boston, MA, 1992.
Molecular Electronics: Devices, Systems and Tools for.. - Butts, DeHon, al. (2002) (Correct)
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D. Gajski, N. Dutt, A. Wu, and S. Lin, High-Level Synthesis: Introduction to Chip and System Design, Kluwer Academic Publishers, 1992.
Compiler-directed Synthesis of Multifunction Loop.. - Fan, Kudlur, Park, Mahlke (Correct)
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D. D. Gajski et al. High-level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publishers, 1992.
DECIDER: A Decision Diagram Based Hierarchical Test.. - Gert Jervan Antti (1998) (Correct)
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D. Gajski, N. Dutt, A. Wu, S. Lin. High-Level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publishers, 1992.
DECIDER: A Decision Diagram Based Hierarchical Test.. - Gert Jervan Antti (1998) (Correct)
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D. Gajski, N. Dutt, A. Wu, S. Lin. High-Level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publishers, 1992.
HW/SW Partitioning Using High Level Metrics - Knerr, Holzer, Rupp (2004) (Correct)
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D. Gajski, N. Dutt, A. Wu, and S. Lin. High-Level Synthesis: introduction to chip and system design. Kluwer Academic Publishers, 1992.
Efficient Integration of Behavioral Synthesis within.. - Cesrio Sugar Moussa (Correct)
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D. Gajski, et al., "High-Level Synthesis: Introduction to Chip and System Design", Kluwer Academic Publishers, Boston, Ma, 1992.
Cycle-Accurate RTL Modeling with Multi-Cycled and.. - Dömer, Gerstlauer, Shin (2002) (Correct)
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D. Gajski, N. Dutt, C. Wu, Y. Lin. High-Level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publishers, 1991.
Unknown - Background We Measured (Correct)
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D. Gajski, N. Dutt, A. Wu, and S. Lin, High-Level Synthesis: Introduction to Chip and System Design, Kluwer Academic Publishers, 1992.
High Level Synthesis from Sim-nML Processor - Basu (1999) (Correct)
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Gajski, D. D., Dutt, N. D., and Wu, A. C.-H. "High Level Synthesis Introduction to Chip and Systems Design". Kluwer Academic Publishers, 1992. 42
Energy and Transient Power Minimization during Behavioral Synthesis - Mohanty (2003) (Correct)
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D. Gajski and N. Dutt, High-Level Synthesis: Introduction to Chip and System Design, Kluwer Academic Publishers, 1992.
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