J. M. P. Cardoso and H. C. Neto. Macro-Based Hardware Compilation of Java Bytecodes into a Dynamic Reconfigurable Computing System. In Proc. of 7  Home/Search   Document Details and Download   Summary   Related Articles   Check

....will then be a costlier approach. We present an approach where the partitioner works in conjunction with the HLS estimator. The estimator provides good design estimates while not performing complete HLS. Previous approaches for temporal partitioning, address partitioning as a scheduling problem [3, 5, 8]. In [7] the user divides the specification into subroutines that are executed on the processor. In [8, 10] the temporal partitioning technique involves partitioning a synthesized gate level design. Since the design to be partitioned is already synthesized, different synthesis options for ....

....reconfiguration while part of the reconfigurable hardware is busy computing (partial reconfiguration) In this paper we accomplish temporal partitioning and scheduling for behavior specifications. Our technique performs design space exploration that cannot be handled by current techniques in [3, 5, 8]. The experimental results show that as HLS techniques exploit the sharing of resources due to the layout flexibility of ASICs, the same can be exploited for reconfigurable processors. 3. MOTIVATION For FPGA based architectural synthesis, the area of the reconfigurable processor is fixed. This ....

J. M. P. Cardoso and Horacio C. Neto, "Macro-Based Hardware Compilation of Java Bytecodes into a Dynamic Reconfigurable Computing System. IEEE Synposium on Field-Programmable Custom Computing Machines, FCCM '99.

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J. M. P. Cardoso, and H. C. Neto, "Macro-Based Hardware Compilation of Java Bytecodes into a Dynamic Reconfigurable Computing System," in Proc. IEEE 7th Symposium on Field-Programmable Custom Computing Machines (FCCM'99), IEEE Computer Society Press, 1999, pp. 2-11.

....algorithm is used. The algorithm fills the available area of the RPU in the increasing order of the ASAP levels. The selection of nodes in the same level is arbitrary and the algorithm switches to another partition when it encounters the first node that does not fit in the current partition. In [19], partitioning algorithms based on the extension of the ASAP or as late as possible (ALAP) leveling algorithms with the selection of a node, in the same ASAP or ALAP level, by a local priority function based on the nodes mobilities have been considered. 19] also shows an algorithm that ....

....not fit in the current partition. In [19] partitioning algorithms based on the extension of the ASAP or as late as possible (ALAP) leveling algorithms with the selection of a node, in the same ASAP or ALAP level, by a local priority function based on the nodes mobilities have been considered. [19] also shows an algorithm that searches recursively in the list of ready nodes so that if a node cannot be mapped to the current partition, other nodes can be considered. However, all the above approaches do not consider both the intercommunication costs and the latency, and the majority of them ....

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J. M. P. Cardoso, and H. C. Neto, "Macro-Based Hardware Compilation of Java Bytecodes into a Dynamic Reconfigurable Computing System, " in Proc. 7 th IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, CA, USA, April 2123, 1999, Kenneth Pocek and Jeffrey Arnold, eds., IEEE Computer Society Press.

....used an existent HLS tool. However, this approach was found not suitable to target reconfigurable devices and, therefore, we decided to develop a new hardware compiler dedicated to reconfigurable computing systems, specially considering architectures with a general processor attached to the RPU [7] (see Figure 1) In this report, we describe the new developments which overcome the identified deficiencies of the HLS systems to handle configurable systems, and which are able to efficiently exploit the virtual hardware concept. The front end starts from Java Bytecodes (after the ....

....model of computation. In order to address this deficiency our compiler uses the graph models shown in Figure 2d for a specific example. These graphs, the DDG (Data Dependency Graph) the CDG (Control Dependency Graph) and the MDG (Merge Dependency Graph) are obtained from the Java bytecodes [7]. The CDG and the DDG are representations firstly used in software compilation Fast Hardware Compilation of Behaviors into an FPGA Based Dynamic Reconfigurable Computing System 6 [19] The MDG and the CDG are much more efficient representations to explore the precomputation of operations in ....

[Article contains additional citation context not shown here]

J. M. P. Cardoso, and H. C. Neto, "Macro-Based Hardware Compilation of Java Bytecodes into a Dynamic Reconfigurable Computing System, " In 7 th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'99), Napa Valley, CA, USA, April 21-23, Kenneth Pocek and Jeffrey Arnold Edt., IEEE Computer Society Press (in Press).

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J. M. P. Cardoso and H. C. Neto. Macro-Based Hardware Compilation of Java Bytecodes into a Dynamic Reconfigurable Computing System. In Proc. of 7

No context found.

J. M. P. Cardoso and H. C. Neto. Macro-Based Hardware Compilation of Java Bytecodes into a Dynamic Reconfigurable Computing System. In Proc. of 7 Symposium on Field Programmable CustomComputing Machines, pages 2--11. IEEE CS, 1999.

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