James E. Bennett. Latency Tolerant Architectures. PhD thesis, Stanford University, 1998. Home/Search Document Details and Download
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Optimum Instruction-level Parallelism (ILP) for Superscalar and .. - Hung, Flynn (1999) (Correct)
....as below. P erformance = N (1 N p 0 L 0 ) 1 O N) 14) We can di erentiate (14) with respect to N to get the optimum ILP width N opt , which is identical to N opt in Scheme C (Equation 12) N opt = 1 p O p 0 L 0 (15) 3. Simulation Results We use the MXS simulator [Ben98], the detailed simulator component of the SimOS simulation environment [RHWG95] to verify our model. MXS employs an execution based simulation method to accurately model a dynamically scheduled processor. The benchmarks are from the SPEC 92 benchmark suite. 6 Figure 3: Performance versus ILP ....
James E. Bennett. Latency Tolerant Architectures. PhD thesis, Stanford University, 1998.
Using Simple Tools to Evaluate Complex Architectural Trade-Offs - Flynn, al. (2000) (1 citation) (Correct)
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J.E. Bennett, "Latency Tolerant Architectures, " PhD thesis, Computer Science Dept., Stanford University, 1998.
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