T. Denk, K. Parhi, "Lower bounds on memory requirements for statically scheduled DSP programs", Journal of VLSI Signal Processing, No.12, pp.247-263, 1996.  Home/Search   Document Not in Database   Summary   Related Articles   Check

.... oriented and they employ a scheduling directed view (see e.g. KuPa87] BMB88] GRV90] SSP92] where the control steps of production consumption for each individual signal are determined beforehand. This applies also for memory register estimation techniques (see e.g. KuPa87] GDW93] DePa96] and their references) This strategy is mainly due to the fact that applications targeted in conventional high level synthesis contain a relatively small number of signals (at most of the order of magnitude 10 3 ) The control data flow graphs addressed are mainly composed of potentially ....

T. Denk, K. Parhi, "Lower bounds on memory requirements for statically scheduled DSP programs", Journal of VLSI Signal Processing, No.12, pp.247-263, 1996.

....allocation of storage units have been scalaroriented and they employ a scheduling directed view (see e.g. 8, 1, 7, 12] where the control steps of production consumption for each individual signal are determined beforehand. This applies also for memory register estimation techniques (see e.g. [8, 6, 5] and their references) This strategy is mainly due to the fact that applications targeted in conventional high level synthesis contain a relatively small number of signals (at most of the order of magnitude 10 3 ) The control data flow graphs addressed are mainly composed of potentially ....

T. Denk, K. Parhi, "Lower bounds on memory requirements for statically scheduled DSP programs", Journal of VLSI Signal Processing, No.12, pp.247-263, 1996.

.... in procedural language compilers has been studied extensively [16, 1] and optimal management of this interaction has been shown to be intractable [14] More recently, the issue of optimal storage allocation has been examined in the context of high level synthesis for iterative DSP programs [11], and code generation for embedded processors that have highly irregular instruction formats and register sets [23, 17] For irregular embedded processors, code generation techniques have also been developed for the purpose of minimizing the amount of memory required to store a program s code [21, ....

T. C. Denk and K. K. Parhi. Lower bounds on memory requirements for statically scheduled dsp programs. J. of VLSI Signal Processing, pages 247{ 264, 1996.

.... allocation in procedural language compilers has been studied extensively [8] 9] and optimal management of this interaction is known to be intractable [10] More recently, the issue of optimal storage allocation has been examined in the context of high level synthesis for iterative DSP programs [11], and code generation for embedded processors that have highly irregular instruction formats and register sets [7] 12] For irregular embedded processors, code generation techniques have also been developed for the purpose of minimizing the amount of memory required to store a program s code ....

T. C. Denk and K. K. Parhi, "Lower bounds on memory requirements for statically scheduled dsp programs," J. of VLSI Signal Processing, pp. 247--264, 1996.

.... and register allocation in procedural language compilers has been studied extensively [10, 1] and optimal management of this interaction is intractable [9] More recently, the issue of optimal storage allocation has been examined in the context of high level synthesis for iterative DSP programs [6], and code generation for embedded processors that have highly irregular instruction formats and register sets 1 Note that this model of buffering maintaining a separate memory buffer for each data flow edge is convenient and natural for code generation. More technical advantages of this ....

T. C. Denk and K. K. Parhi. Lower bounds on memory requirements for statically scheduled dsp programs. J. of VLSI Signal Processing, pages 247-- 264, 1996.

.... allocation in procedural language compilers has been studied extensively [9] and optimal management of this interaction has been shown to be intractable [8] More recently, the issue of optimal storage allocation has been examined in the context of high level synthesis for iterative DSP programs [5], and code generation for embedded processors that have highly irregular instruction formats and register sets [13, 10] These efforts do not address the challenges of keeping code size costs manageable in general SDF graphs, in which actor production and consumption parameters may be arbitrary. ....

T. C. Denk and K. K. Parhi. Lower bounds on memory requirements for statically scheduled dsp programs. J. of VLSI Signal Processing, pages 247--264, 1996.

.... language compilers has been studied extensively [ Hsu87; ASU86 ] and optimal management of this interaction has been shown to be intractable [ GJ79 ] More recently, the issue of optimal storage allocation has been examined in the context of high level synthesis for iterative DSP programs [ DP96 ] and code generation for embedded processors that have highly irregular instruction formats and register sets [ Me95; KNDK96 ] However, because of their focus on fine grain scheduling, the above efforts apply to a homogeneous data flow model that is, a model in which each computation ....

T. C. Denk and K. K. Parhi. Lower bounds on memory requirements for statically scheduled dsp programs. J. of VLSI Signal Processing, pages 247--264, 1996.

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