Chen, C., and Sarrafzadeh M. Provably good algorithm for low power consumption with dual supply voltages. in Proc. of ICCAD'99 (San Jose CA, 1999), 76-79. Home/Search Document Details and Download
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What is the Limit of Energy Saving by Dynamic Voltage Scaling? - Qu (2001) (3 citations) (Correct)
....(e.g. the supply voltages can be changed simultaneously with no physical constraints) 16] However, it takes time for system to reach the steady state at a new voltage level. This motivates a lot of work on multiple voltage systems where only several pre designed supply voltages are available[4, 5, 6, 9, 14, 15]. Our work is motivated by the recent implementation of microprocessor that can adjust its operating speed at run time[1] This is clearly a different DVS system from the above two: it considers physical constraints on voltage but does not restrict it to be at certain pre defined levels. To the ....
....voltage to save energy. Johnson and Roy [10] propose a datapath scheduling algorithm which iteratively reduces the operating voltage until no schedule slack remains. They have also discussed the additional power consumed by the DC DC converters and the area penalties. Chen and Sarrafzadeh [6] give a lower bound of power consumption with dual supply voltage. They relate this problem to the maximal weighted independent set problem and solve the latter by a provably good algorithm. For the ideal DVS system, Yao et al. 16] provide an optimal static scheduling algorithm for a set of ....
C. Chen and M. Sarrafzadeh. "Provably Good Algorithm for Low Power Consumption with Dual Supply Voltages," ICCAD'99: IEEE/ACM International Conference on Computer-Aided Design, pp. 76-79, November 1999.
Physical Design with Multiple On-Chip Voltages - Chunhong Chen Dept Self-citation (Chen) (Correct)
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Chen, C., and Sarrafzadeh M. Provably good algorithm for low power consumption with dual supply voltages. in Proc. of ICCAD'99 (San Jose CA, 1999), 76-79.
On Gate Level Power Optimization Using Dual-Supply Voltages - Chen, Srivastava.. (2001) (3 citations) Self-citation (Chen Sarrafzadeh) (Correct)
....of slacks in a given circuit. In order to get the maximum power reduction while maintaining the timing performance of the circuit, we relate the power optimization to the maximal weighted independent set (MWIS) problem and propose a fast heuristic algorithm to predict the optimum supply voltage [21]. Then, based on predicted supply voltages, we develop an effective algorithm to allow as many gates as possible working at . Considering the possible power penalty of the LCs at the interface of and , we target minimizing the number of LCs by using what we call the constrained ....
C. Chen and M. Sarrafzadeh, "Provably good algorithm for low power consumption with dual supply voltages," in Proc. Int. Conf. Comput.- Aided Design (ICCAD), San Jose, CA, Nov. 1999, pp. 76--79.
Potential Slack: An Effective Metric of Combinational.. - Chen, Yang, Sarrafzadeh (2000) (3 citations) Self-citation (Chen Sarrafzadeh) (Correct)
....Theorem 2: The time complexity of MISA is O (K n 3 ) where n and K are the number of nodes and the number of different slacks in a given graph, respectively. 3. 3 Application to Gate Sizing Potential slack can be used for a class of delay constrained area power optimization problems [5 7, 12, 13]. Given the timing constraints which represent circuit performance requirement, gate sizing problem is to find a set of gates nodes such that their physical sizes can be reduced (by using smaller cell instances from a target library) for area power minimization without violating timing ....
C. Chen and M. Sarrafzadeh, "Provably Good Algorithm for Low Power Consumption with Dual Supply Voltages," in Proceedings of ICCAD, pp.76-79, 1999.
Power Optimization of Delay Constrained Circuits - Nayak, Haldar, Banerjee.. Self-citation (Chen Sarrafzadeh) (Correct)
....slack does not imply that the slacks of all its transitive fanins are also small. A linear 7 programming approach was also proposed [18] to address the dual voltage problem. However, it is based on the delay balanced configurations whose generation requires very expensive computation cost. In [6, 19], a Two Voltage Power Optimization (TVPO) algorithm is proposed to reduce power by translating the power optimization problem into the Maximal Weighted Independent Set (MWIS) problem and allowing as many gates as possible working at V low . The number of level converters at the boundary of ....
C. Chen and M. Sarrafzadeh , Provably Good Algorithm for Low Power Consumption with Dual Supply Voltages, Proc. of International Conference on Computer-Aided-Design, 1999, pp. 76-79
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