K.Usami et al., Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques, ACM/IEEE Design Automation Conference, pp.483-488, June 1998 16 Home/Search Document Details and Download
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Power Optimization of Delay Constrained Circuits - Anshuman Nayak Malay (Correct)
.... gate s input capacitance equal to 0:097 fF and output resistance equal to 23:8k Omega [15] 3 Voltage Scaling Reducing the supply voltage, or voltage scaling (VS) promises to be an effective low power technique since the dynamic power consumption is quadratically related to the supply voltage [2 8,17]. While reducing the supply voltage of a whole circuit suffers from circuit speed loss, a low voltage applied only to non critical paths of the circuit does not necessarily lead to performance degradation. The major overhead in using different supply voltages at different parts of a circuit is ....
K.Usami et al., Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques, ACM/IEEE Design Automation Conference, pp.483-488, June 1998 16
An Integrated Circuit/Architecture Approach to.. - Yang, Powell.. (2001) (30 citations) (Correct)
....current proposals for energy efficient cache architectures [12,2,1] only target reducing dynamic energy and do not impact leakage energy. There are a myriad of circuit techniques to reduce leakage energy dissipation in transistors circuits (e.g. multi threshold [30,25,17,28] or multi supply [27] voltage designs, dynamic threshold [29] or dynamic supply [5] voltage designs, and transistor stacking [32] These techniques, however, typically impact circuit performance and are only applicable to circuit sections that are not performance critical [10] Second, unlike embedded processor ....
....from assuming a size close to the required size, offsetting the gains from reduced switching overhead. 6 Related work There are a number of previous studies that have focused on circuit level only techniques to reduce leakage power. Techniques such as multi threshold [30,25,17] or multi supply [27] voltage designs, dynamic threshold [29] or dynamic supply [5] voltage designs, and transistor stacking [32] have been used to reduce leakage energy dissipation while maintaining high performance. However, circuit level techniques that apply leakage reduction ignore application architectural ....
K. Usami and M. Horowitz. Design methodology of ultra lowpower mpeg4 codec core ecploiting voltage scaling techniques. In Proceedings of the 35th Design Automation Conference, pages 483--488, 1998.
Power Optimization of Delay Constrained Circuits - Nayak, Haldar, Banerjee.. (Correct)
.... gate s input capacitance equal to 0:097 fF and output resistance equal to 23:8k Omega [15] 3 Voltage Scaling Reducing the supply voltage, or voltage scaling (VS) promises to be an effective low power technique since the dynamic power consumption is quadratically related to the supply voltage [2 8,17]. While reducing the supply voltage of a whole circuit suffers from circuit speed loss, a low voltage applied only to non critical paths of the circuit does not necessarily lead to performance degradation. The major overhead in using different supply voltages at different parts of a circuit is ....
K.Usami et al., Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques, ACM/IEEE Design Automation Conference, pp.483-488, June 1998
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