E.S.Ochotta, "Synthesis of High Performance Analog Cells in ASTRX /OBLX", Ph.D Dissertation, Feb 1994, CMU.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....bad circuit sizing. This characterization mechanism is geared more towards assisting the manual design of analog circuits, rather than automatic CAD tools. A typical analog synthesis flow consists of a high level constraint transformation step followed by circuit and layout synthesis steps [6, 8, 9]. Crucial to such a top down design method is an interfacing mechanism to communicate the specifications and constraints on the design elements used at one level to those at the next level. This task of transforming the high level specifications onto module parameters is called Constraint ....

E.S.Ochotta, "Synthesis of High Performance Analog Cells in ASTRX /OBLX", Ph.D Dissertation, Feb 1994, CMU.

.... problem are being developed in the reinforcement learning community under the rubric of value function approximation [2] Alternatives to value function approximation include learning from rollouts (e.g. 1] and treating the evaluation function weights as parameters to meta optimize (e.g. [6]) as described above in the section on algorithm tuning. Our survey includes summaries of ve studies on learning evaluation functions for optimization: McGovern, Moss, and Barto (x ) learn an evaluation function for move selection in the domain of optimizing compiled machine code, comparing ....

E. Ochotta. Synthesis of High-Performance Analog Cells in ASTRX/OBLX. PhD thesis, CMU Electrical and Computer Engineering, 1994.

....simulated annealing, and domainspecific algorithms where applicable. The hillclimbing runs accepted equi cost moves and restarted whenever patience consecutive moves produced no improvement. The simulated annealing runs made use of the successful modified Lam adaptive annealing schedule (Ochotta, 1994, 4.5) its parameters were hand tuned to perform well across the whole range of problems but not exhaustively optimized for each individual problem instance. On each instance, all algorithms were held to the same number M of total search moves considered, and run N times. Space limits prevent ....

....The lack of such constraints means that less information for training the function can be gleaned from a simulation run; however, not having to meet the Bellman constraints may actually make learning easier. An example application of meta optimization for combinatorial optimization may be found in (Ochotta, 1994). We believe that new memory based stochastic optimization techniques (Moore Schneider, 1996; Moore, Schneider, Boyan, Lee, 1998) can significantly reduce the computational requirements of direct meta optimization. Whether direct meta optimization methods or Stage like methods ultimately ....

Ochotta, E. (1994). Synthesis of High-Performance Analog Cells in ASTRX/OBLX. Ph.D. thesis, CMU Electrical and Computer Engineering.

....the constraint allocator should have the capacity to detect the inability of the design to meet the system level constraints, and thus back track to the previous step in the synthesis process. This is precisely what our constraint allocator does. The underlying circuit synthesis tool ASTRX OBLX [7] from Carnegie Mellon University, makes use of the values obtained from the constraint allocator to synthesize a design which meets the constraints. 3 Architecture of VASE I VASE I (VHDL AMS Synthesis Environment) is a mixedsignal synthesis system being developed at the University of Cincinnati. ....

....constraints produced by the constraint allocator. The layout synthesis tools accept the sized circuit as the input and generate a layout for the same. The circuit and layout synthesis tools being used in VASE are ASTRX OBLX and KOAN ANAGRAM which are a part of the ACACIA system developed at CMU [7]. The RTL design for the digital part produced by DSS is processed through the LAGER IV tool set to produce the layout of the digital part. These layouts are then integrated in a final layout integration step. 4 Constraint Satisfaction Problems A CSP is composed of a finite set of variables, ....

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E.S.Ochotta, "Synthesis of High Performance Analog Cells in ASTRX/OBLX", Ph.D Dissertation, Feb 1994, CMU.

....space within which the circuit synthesis tool can conduct it s search. We present experimental evidence showing the impact of pruning the search space of the circuit synthesis tool. The pruning technique could be used with any optimization based circuit synthesis tool. We have used ASTRX OBLX [8] to demonstrate this technique. This constraint transformation method forms a part of the VASE (VHDL AMS Synthesis Environment) 13] mixed signal synthesis system being developed at the University of Cincinnati. 2 Motivation The parameter space is defined to be the space having as many ....

E.S.Ochotta, "Synthesis of High Performance Analog Cells in ASTRX /OBLX", Ph.D Dissertation, Feb 1994, CMU.

....run slowly and may even be unstable. I will evaluate several original value function approximation algorithms tailored for combinatorial optimization domains. The meta optimization approach, which has also been applied to game playing [ Pollack et al. 1996 ] and combinatorial optimization [ Ochotta, 1994 ] is conceptually simpler: we assume a fixed parametric form for the evaluation function and optimize it directly. These methods, lacking the theoretical advantages of dynamic programming, have been ignored by the reinforcement learning community; however, recent advances in local ....

....and presents another new algorithm. The second approach, meta optimization, is conceptually simpler: we assume a fixed parametric form for the evaluation function and optimize it directly. This approach was also used by Samuel [1959] and has been applied in the simulated annealing community [Ochotta, 1994]. Meta optimization methods, lacking the theoretical advantages of dynamic programming, have been largely ignored by the reinforcement learning community; however, recent advances in local optimization [Moore and Schneider, 1996] may help make them superior to reinforcement learning in practice. ....

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E. Ochotta. Synthesis of High-Performance Analog Cells in ASTRX/OBLX. PhD thesis, Carnegie Mellon University Department of Electrical and Computer Engineering, April 1994.

....no heuristic penalties in its schedules, so that figure is a profit in real dollars. Simulated annealing, greedy exploration, and Memory Based RTDP are run as described in the previous sections. The simulated annealing runs made use of the successful modified Lam adaptive annealing schedule [8]. The poor result from greedy shows that generating trajectories based solely on the one step cost of configurations is not an effective way to search even when compared to a random search method such as simulated annealing. The search efficiency gained by computing a value function is shown by ....

E. Ochotta. Synthesis of High-Performance Analog Cells in ASTRX /OBLX. PhD thesis, Carnegie Mellon University Department of Electrical and Computer Engineering, April 1994.

....constraints are given to the circuit synthesis tool, which performs transistor sizing based on the specified performance constraints. The layout synthesis tool takes the sized circuit as input and produces the layout. The circuit and layout synthesis tools being used in VASE are ASTRX OBLX [6] and KOAN ANAGRAM which are a part of the ACACIA system from Carnegie Mellon University. 7. Layout Integration: The mixed signal system s layout is produced by integrating the analog and digital layouts. This step is right now being done manually. 2.1 Analog Component Library The analog ....

E.S. Ochotta, "Synthesis of High Performance Analog Cells in ASTRX/OBLX", Ph.D. Dissertation, Feb 1994.

....penalties in its schedules, so that figure is a profit in real dollars. The simulated annealing, greedy exploration, and Memory based RTDP algorithms are run as described in the previous sections. The simulated annealing runs made use of the successful modified Lam adaptive annealing schedule [ Ochotta, 1994 ] Memory based RTDP used kernel regression with a kernel width of 2 Gamma5 of the range of each state variable, and used KDtrees for efficiency [ Moore et al. 1997 ] Boltzmann exploration (without cooling) was used for the deterministic case, but proved unnecessary in the stochastic case ....

E. Ochotta. Synthesis of HighPerformance Analog Cells in ASTRX/OBLX. PhD thesis, Carnegie Mellon University Department of Electrical and Computer Engineering, April 1994.

....simulated annealing, and domain specific algorithms where applicable. The hillclimbing runs accepted equi cost moves and restarted whenever patience consecutive moves produced no improvement. The simulated annealing runs made use of the successful modified Lam adaptive annealing schedule (Ochotta 1994, x4.5) its parameters were hand tuned to perform well across the whole range of problems but not exhaustively optimized for each individual problem instance. On each instance, all algorithms were held to the same number M of total search moves considered, and run N times. Bin packing The first ....

Ochotta, E. 1994. Synthesis of High-Performance Analog Cells in ASTRX/OBLX. Ph.D. Dissertation, Carnegie Mellon University Department of Electrical and Computer Engineering.

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E.S.Ochotta, "Synthesis of High Performance Analog Cells in ASTRX /OBLX", Ph.D Dissertation, Feb 1994, CMU.

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Ochotta 94a E. Ochotta, Synthesis of High-Performance Analog Cells in ASTRX/OBLX. PhD Thesis, Carnegie Mellon University, 1994.

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E. Ochotta. Synthesis of High-Performance Analog Cells in ASTRX /OBLX. PhD thesis, Carnegie Mellon University Department of Electrical and Computer Engineering, April 1994.

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