J. Tseng. Energy-efficient register file design. Master's thesis, Massachusetts Institute of Technology, December 1999. Home/Search Document Details and Download
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A Low-Power 32 bit Datapath Design - Heo (2000) (1 citation) (Correct)
....a split shifter, in terms of delay and power. We use benchmarks to get more realistic activation patterns for energy analysis. We show that the barrel shifter is a better choice than any log shifter. We include the register file in our energy breakdowns, but the design is taken from earlier work [17]. Finally, in Chapter 5, we analyze the datapath energy using our energy model and benchmarks. We perform energy breakdown by components and show that basic building 17 blocks such as flipflops, latches, and muxes, account for over half the total energy (56 ) We also try energy breakdown by ....
....ALU is arguably the most important block in the datapath. It performs arithmetic operations like addition and subtraction, load and store address calculation, and logical operations such as XOR, OR, AND, and NOR. SPECint95 benchmarks results indicate that over 70 of instructions use the ALU block [17]. Therefore, the ALU is one of the hottest spots in the datapath. However, applying low power techniques to the ALU is not straightforward since it is also one of the main speed bottlenecks in the datapath. For this project, we chose an adder design which consumes the least power while satisfying ....
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J. Tseng. Energy-efficient register file design. Master's thesis, Massachusetts Institute of Technology, December 1999.
Energy-Efficient Register Access - Jessica Tseng And (2000) (3 citations) Self-citation (Tseng) (Correct)
....interact for a pipelined RISC processor running large benchmark programs. The paper is structured as follows. Section 2 describes our experimental methodology. Sections 3 10 describes our base case register file design and the seven energy saving techniques in detail: modified storage cell [7] which avoids bitline discharge for zero bits, precise read control [1, 7] which avoids fetching unused operands, latch clock gating which disables latch clocks when operands are not needed, bypass skip [1, 7] which turns off regfile reads when regfile bypass circuitry will supply the value, ....
....The paper is structured as follows. Section 2 describes our experimental methodology. Sections 3 10 describes our base case register file design and the seven energy saving techniques in detail: modified storage cell [7] which avoids bitline discharge for zero bits, precise read control [1, 7] which avoids fetching unused operands, latch clock gating which disables latch clocks when operands are not needed, bypass skip [1, 7] which turns off regfile reads when regfile bypass circuitry will supply the value, bypass R0 [7] which treats accesses to R0 separately, split bitline [7] which ....
[Article contains additional citation context not shown here]
J. Tseng. Energy-efficient register file design. Master's thesis, Massachusetts Institute of Technology, December 1999.
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