J. Rose, A.E. Gamal, and A. Sangiovanni-Vincentelli. Architecture of FieldProgrammable Gate Arrays. Proceedings of the IEEE, July 1993. 81(7): pp. 10131029.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....computing. Our Hybrid System Architecture Model (HySAM) is presented in Section V and example dynamic precision variation algorithm is described. Section VI provides the concluding remarks and provides references for further study. II. Reconfigurable Computing Programmable Gate Arrays (FPGAs) [1]. FPGAs consist of a matrix of logic blocks and an interconnection network. The functionality of the logic blocks and the connections in the interconnection network can be modified by downloading bits of configuration data onto the hardware. Currently, hybrid architectures which integrate ....

....permit unlimited reconfiguration. These versatile devices have been used to build processors and coprocessors whose internal architecture as well as interconnections can be configured to match the needs of a given application. For a detailed architectural survey of FPGAs and related systems, see [1], 5] 17] Typically, the application requirements increase at a rate faster than the increase in the size of logic resources on most FPGA devices. FPGA architectures also have limits on the I O capability due to the limitation on the number of I O pins on the device. To map large applications ....

J. Rose, A. El Gamal, and A. Sangiovanni-Vincentelli, "Architecture of Field Programmable Gate Arrays," Proceedings of the IEEE, July 1993.

....lower turn around time and higher flexibility, the later has a number of advantages due to its lower cost in mass production, higher level of achievable performances, and lower power. In the last 10 years field programmable gate arrays (FPGA) have become a popular design implementation medium [13]. While numerous synthesis techniques targeting FPGAs have been developed [14] synthesis methods for ASPPs have been addressed only tangenttally. However, the market trends clearly indicate a rapidly gr.wing need for efficient synthesis technologies of ASPP designs. Almost all major semiconductor ....

J. Rose, A. E1 Gamal, A. Sangiovanni-Vincentelli, "Architecture of FieldProgrammable Gate Arrays", Proc. IEEE, Vol. 81, No. 7, pp. 1013-1029, 1993.

....further phase, using 48 test vectors and 38 I DDQ measurements. Index Terms Testing, FPGA, bridging fault, I DDQ test, configurable logic blocks, programming phase. ###p### 1INTRODUCTION IELD Programmable Gate Arrays (FPGAs) 1] [2] are widely used today for rapid system development and are available from many vendors [3] 4] 5] 6] Using Xilinx terminology, FPGAs consist of an array of configurable logic blocks (CLBs) to implement logic functions and storage, input output blocks (IOBs) to provide off chip ....

# J. Rose, A.E. Gamal, and A. Sangiovanni-Vincentelli, "Architecture of Field Programmable Gate Arrays," Proc. IEEE, vol. 81, no. 7, pp. 1,013-1,029, July 1993.

....2.7. By filling in the table with the right bits, any four input logic function can be realized. Various studies have suggested that four inputs is a good size for these lookup tables, trading o# utility (how powerful the blocks are) against utilization (what fraction of their power ends up idle) [65, 66]. Logic blocks in actual FPGAs tend to be more complex than a single lookup table; Figure 2.8 has a similar diagram for a Xilinx 4000 series logic block, which has two fourinput lookup tables and an extra three input table, for a total of eleven bits of input and four bits of output [71, 81] ....

....bearing on array design is the extent to which FPGAs are normally dominated by their configurable networks, both in terms of circuit area and delay. In 1993, Rose et al. asserted that the area for routing is usually larger than the active area . representing from 70 to 90 of the total area [66]. And the significance of the network only increases as FPGAs grow. Six years later, Betz and Rose have reconfirmed that the delay of a circuit implemented in an FPGA is mostly due to routing delays, rather than logic block delays, and most of an FPGA s area is devoted to programmable routing ....

Jonathan Rose, Abbas El Gamal, and Alberto Sangiovanni-Vincentelli. Architecture of field-programmable gate arrays. Proceedings of the IEEE, 81(7):1013--1029, July 1993.

....of reconfigurable computing. Instead, it hopes to serve as an introduction to this rapidly evolving field, bringing interested readers quickly up to speed on developments from the last half decade. Those interested in further background can find coverage of older techniques and systems elsewhere [Rose93, Smith97, Hauck96, Hauck98d]. 2 Technology Reconfigurable computing as a concept has been in existence for quite some time [Estrin63] Even general purpose processors use some of the same basic ideas, such as reusing computational components for independent computations, and using multiplexers to control the routing ....

....computing. Hardware concepts applying specifically to architectures designed for reconfigurable computing, as well as variations on the generic FPGA description provided here are discussed following this section. More detailed surveys of the FPGA architectures themselves can be found elsewhere [Brown92a, Rose93]. Since the introduction of FPGAs in the mid 1980 s there have been many different investigations into what computation element(s) should be built into the array [Rose93] One could consider FPGAs that were created with PAL like product term arrays, or multiplexer based functionality, or even ....

[Article contains additional citation context not shown here]

J. Rose, A. El Gamal, A. Sangiovanni-Vincentelli, "Architecture of Field-Programmable Gate Arrays", Proceedings of the IEEE, Vol. 81, No. 7, pp. 1013-1029, July 1993.

....support active computation in a much smaller portion of the chip. Reconfigurable computing can have significantly higher computational power efficiency compared with conventional microprocessors and ASICs [54] Reconfigurable architectures have evolved from Field Programmable Gate Arrays (FPGAs) [65]. FPGAs consist of a matrix of logic blocks and interconnection network. The functionality of the logic blocks and the connections in the interconnection network can be modified by downloading bits of configuration data onto the hardware. Currently, hybrid architectures which integrate ....

....permit unlimited reconfiguration. These versatile devices have been used to build processors and coprocessors whose internal architecture as well as interconnections can be configured to match the needs of a given application. For a detailed architectural survey of FPGAs and related systems, see [18, 40, 65]. 19 Configuration SRAM Interconnect FPGA FPGA FPGA FPGA Memory Memory Memory Memory D Multi FPGA Board Logic Block FF FPGA 4 LUT Figure 2.1: Typical FPGA Board, Device and Logic block architecture 20 Current and future generation reconfigurable devices ameliorate the reconfiguration ....

J. Rose, A. E. Gamal, and A. Sangiovanni-Vincentelli. Architecture of Field Programmable Gate Arrays. Proceedings of the IEEE, July 1993.

.... Bioccelerator La machine Bioccelerator [7] developpee au Weiztmann Institute of Science, en Israel, est une machine specialisee dans l acceleration de certains programmes du progiciel Gcg [8] Genetics Computer Group) Le coeur de la machine est constituedecircuits logiques reconfigurables [14] (Fpga : Field Programmable Gate Array) Cette machine n est donc pas dediee a un algorithme particulier : en modifiant les configurations associes aux Fpga, les structures de la machine peuvent etre directement adaptees a un algorithme donne. Par contre, le temps d implantation et de mise au ....

J. Rose, A. El Gamal, and A. Sangiovanni Vincentelli. Architecture of Field-Programmable Gate Arrays. Proceedings of the IEEE, 81(7):1013--1029, jul 1993.

....the underlying hardware, could still participate in the high level design process. For general purpose computers the answer of course is yes, but for the hardware family that originated in the programmable logic device (PLD) 1] and has now encompassed complex eld programmable gate arrays (FPGAs) [2] the answer has until recently been no, principally because current software CAD tools do not suciently abstract from the hardware. FPGAs were originally thought of simply as weakly programmable glue logic, and CAD tools were designed bottom up to support the hardware design process. Currently ....

J. Rose, A. El Gamal, and A. Sangiovanni-Vincentielli. Architecture of Field-Programmable Gate Arrays. Proceedings of IEEE, pages 1013-1028, 1993.

....approach. Architecturally, an FPGA is characterized by three types of building blocks, namely, i) Configurable Logic Blocks (CLBs) ii) Input Output Blocks (IOBs) and (iii) Interconnection Networks. The structure of a CLB can be as simple as a transistor to as complex as a microprocessors [193]. The CLBs can be arranged in a row, or, more commonly, in a matrix form. A typical CLB of Xilinx 4000 series FPGA is shown in Figure 3.2. The total number of CLBs on a FPGA also varies from vendor to vendor. In Xilinx 4010, there are 400 CLBs. The IOBs provide an interaction with the external ....

J. Rose, A. E. Gammal, and A. Sangiovanni-Vincentelli. Architecture of fieldprogrammable gate arrays. Proceedings of the IEEE, 81(7):1013--1029, July 1993.

....application speci c hardware circuits to be created on demand to meet the computing and interconnect requirements of an application. Moreover, these hardware circuits can be dynamically modi ed partially or completely in time and in space based on the requirements of the operations under execution [5, 13]. Private key cryptographic algorithms seem to t extremely well with the characteristics of the FPGAs. The ne granularity of FPGAs matches extremely well the operations required by private key cryptographic algorithms such as bitpermutations, bit substitutions, look up table reads, and boolean ....

....for several application domains such as signal image processing, graph algorithms, genetic algorithms, and cryptography among others. The basic feature underlying FPGAs is the programmable logic element which is realized by either using anti fuse technology or SRAM controlled transistors. FPGAs [5, 13] have a matrix of logic cells overlaid with a network of wires. Both the computation performed by the cells and the connections between the wires can be con gured. Current devices mainly use SRAM to control the con gurations of the cells and the wires. Loading a stream of bits onto the SRAM on the ....

J. Rose, A. El Gamal, and A. Sangiovanni-Vincentelli, \Architecture of Field Programmable Gate Arrays", Proceedings of the IEEE, July 1993.

....[Xilinx94] and a 3 input LUT (right) There are many different types of FPGAs, with many different structures. Instead of discussing all of them here, which would be quite involved, this section will present two representative FPGAs. Details on many others can 4 be found elsewhere [Brown92, Rose93, Chan94, Jenkins94, Trimberger94, Oldfield95] Note that reconfigurable systems can often employ non FPGA reconfigurable elements; These will be described in section 5. I O Blocks I O B l o c k s I O B l o c k s I O Blocks Figure 4. The Xilinx 4000 series FPGA structure ....

J. Rose, A. El Gamal, A. Sangiovanni-Vincentelli, "Architecture of Field-Programmable Gate Arrays", Proceedings of the IEEE, Vol. 81, No. 7, pp. 1013-1029, July 1993.

....s equences biologiques. Cette description n est pas exhaustive. Elle est cependant repr esentative de l etat de l art actuel. Les deux premi eres font appel a des puces sp ecialis ees concues sp ecifiquement pour ces machines ; les deux suivantes int egrent des circuits logiques reconfigurables [15] dans lesquels un algorithme peut etre cabl e et modifi e a volont e ; la derni ere est une approche mixte et est un projet de recherche men e conjointement entre l Irisa a Rennes et l Inria a Rocquencourt. 3 Quelques machines d edi ees a l analyse de s equences biologiques 3.1 La machine ....

.... La machine Bioccelerator [6] d evelopp ee au Weiztmann Institute of Science, en Israel, est une machine sp ecialis ee dans l acc el eration de certains programmes du progiciel Gcg [9] Genetic Computer Group s) Le coeur de la machine est constitu e de circuits logiques reconfigurables [15] (Fpga : Field Programmable Gate Array) Un Fpga, ou circuit logique reconfigurable, est un composant electronique compos e d une matrice de blocs el ementaires dans lesquels une fonction logique peut etre programm ee. Ce composant dispose de ressources de routage ( egalement programmables) ....

J. Rose, A. El Gamal, and A. Sangiovanni-Vincentelli. Architecture of Field-Programmable Gate Arrays. Proceedings of the IEEE, 81(7):1013-- 1029, jul 1993.

....permit unlimited reconfiguration. These versatile devices have been used to build processors and coprocessors whose internal architecture as well as interconnections can be configured to match the needs of a given application. For a detailed architectural survey of FPGAs and related systems, see [14, 30, 52]. Current and future generation reconfigurable devices ameliorate the reconfiguration cost by providing partial and dynamic reconfigurability [25, 31, 53, 55, 64] In partial reconfiguration, it is possible to modify the configuration of a part of the device while the configuration of the ....

Jonathan Rose, Abbas El Gamal, and Alberto Sangiovanni-Vincentelli. Architecture of Field Programmable Gate Arrays. Proceedings of the IEEE, July 1993.

....describes an integrated coprocessor for accelerating character string comparisons for spelling correction. The design is based on a truncated 2 D systolic array of 69 processing elements. In the last few years many projects have been started based on field programmable gate arrays (FPGAs) Rea93] This flexible hardware technology supports the development of application specific coprocessors. At least prototyping can be done very easily and rather quickly on FPGA basis. Moreover, some types of FPGAs are reconfigurable. This allows the construction of coprocessors which can be rapidly ....

....programmable logic devices (PLDs) and (ii) field programmable gate arrays (FPGAs) PLDs have a rigid structure consisting of programmable AND arrays, programmable OR gates, and flip flops. FPGAs combine the array structure of mask programmable gate arrays with the programmability of PLDs [Rea93] Further, FPGAs are distinguished according to their architectures and their programming methods. Examples for FPGA architectures are the matrix based architecture, the row based architecture, extended PLA, and sea of gates. The programming method can be SRAM based, EEPROM based, or ....

Jonathan Rose et al. Architecture of Field Programmable Gate Arrays. Proceedings of the IEEE, 7(81):1013--1029, June 1993. 100

....The placement problem is especially important in designs 6 using such devices, because fixed routing resources make it difficult to achieve 100 automatic routing. Automated FPGA layout generation can be divided into four major phases, partitioning , technology mapping , placement and routing (Rose et al. 1993). Partitioning is used for very large logic circuits that require multiple FPGA chips. In technology mapping phase, a logic circuit is transformed to an optimized, generic logic input format that consists of CLBs and IOBs. In the placement phase, the circuit that is formed in the ....

Rose, J., Elgamal, A. E., & Sangiovanni-Vincentelli, A. (1993). Architecture of field-programmable gate-array, Proceedings of IEEE, 81, 1013--1029.

....by using off the shelf components in each processor board of the testbed (processors, memory chips, and bus interface) but leaving cache, memory and coherence controllers programmable. FPGAs (Field Programmable Gate Arrays) implement these controllers. These chips are reconfigured by software [13]. The testbed is made of nine SPARC processors (eight execution processors and one I O processor) connected to a Futurebus backplane and is clocked at 10 MHz. The number of clocks in each processor clock (pclock) is variable (it depends on the complexity of the mechanisms to simulate) but is ....

Rose, J. et al., "Architecture of Field-Programmable Gate Arrays", Proceedings of the IEEE, Vol. 81, No.7, July 1993.

....reconfigurable computing. Instead, it hopes to serve as a brief introduction to this rapidly evolving field, bringing interested readers quickly up to speed on developments from the last half decade. Those interested in further background can find coverage of other techniques and systems elsewhere [1, 2, 3, 4] Field Programmable Gate Arrays FPGAs were originally created to serve as a hybrid device between PALs and Mask Programmable Gate Arrays (MPGAs) Like PALs, they are fully electrically programmable, meaning that the Non Recurring Engineering (NRE) costs are amortized, and they can be customized ....

J. Rose, A. El Gamal, A. Sangiovanni-Vincentelli, "Architecture of Field-Programmable Gate Arrays", Proceedings of the IEEE, Vol. 81, No. 7, pp. 1013-1029, July 1993.

....of reconfigurable computing. Instead, it hopes to serve as an introduction to this rapidly evolving field, bringing interested readers quickly up to speed on developments from the last half decade. Those interested in further background can find coverage of older techniques and systems elsewhere [Rose93, Smith97, Hauck98d] Field Programmable Gate Arrays FPGAs were originally created to serve as a hybrid device between PALs and Mask Programmable Gate Arrays (MPGAs) Like PALs, they are fully electrically programmable, meaning that the Non Recurring Engineering (NRE) costs are amortized, and they can be customized ....

J. Rose, A. El Gamal, A. Sangiovanni-Vincentelli, "Architecture of Field-Programmable Gate Arrays", Proceedings of the IEEE, Vol. 81, No. 7, pp. 1013-1029, July 1993.

....1 Introduction Les composants FPGA (Field Programmable Gate Array) sont apparus vers le milieux des ann ees 80. Ce sont des circuits digitaux programmables que l on peut reconfigurer a volont e. Un meme support physique peut ainsi supporter, a des instants diff erents, diverses architectures [1]. La structure classique d un tel composant se pr esente comme une matrice de cellules el ementaires inter connect ees via des commutateurs programmables. Une cellule abrite une ou plusieurs fonctions logiques programmables et inclut egalement au moins un el ement de m emorisation (un ....

J. Rose, A. Gamal, A. Sangiovanni-Vincentelli. Architecture of Field-Programmable Gate Array. Proceedings of the IEEE, vol 81, No 7, July 1993.

....of the chip. These are connected to the pins of the package and can be programmed as input, output, or disabled. The XC3000 LCAs come in various sizes from 64 to 320 LCAs, corresponding to 2000 to 9000 gate equivalents. For a more comprehensive introduction to FPGAs the tutorial by Rose et. al [1] is recommended. 2.3. Architectures In itself an FPGA may be used as a component in a signal processing system. An example of such use is given by Klock et. al [2] where a filter bank is implemented in a Xilinx XC4000 Chip. Such ad hoc use of FPGAs will probably become frequent in the future. In ....

J. Rose, A. el Gamal, and A. SangiovanniVincentelli, Architecture of Field-Programmable Gate Arrays, Proc. IEEE, Vol. 81, No. 7, 1993, 00 1013--1029.

....Also, unlike the SRAM technology, EPROM or EEPROM requires no external permanent memory to program the chip at power up. However, the EPROM EEPROM technology suffers from some drawbacks such as relatively high ON resistance, high static power consumption, and complicated manufacturing processes [28]. 2.4 Summary of Programming Technologies Table 1 compares the properties of SRAM, ONO antifuse, amorphous antifuse, EPROM, and EEPROM programming technologies based on a 0.65 m process technology; it gives the name of the technology, the relative complexity of manufacturing process (measured ....

....of SRAM, ONO antifuse, amorphous antifuse, EPROM, and EEPROM programming technologies based on a 0. 65 m process technology; it gives the name of the technology, the relative complexity of manufacturing process (measured in the number of extra processing steps required beyond standard CMOS [28]) the availability of reprogramming, the approximate relative size of the switch, the series resistance of an ON switch, the parasitic capacitance of an OFF switch, the relative degree of power consumption, and the volatility of the configuration. Programming SRAM ONO Amorphous EPROM EEPROM ....

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J. Rose, A. El Gamal, A. Sangiovanni-Vincentelli, Architecture of field-programmable gate arrays, Proc. of the IEEE, 81 (7), pp. 1013--1029, July 1993.

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J. Rose, A. El Gamal, and A. Sangiovanni-Vincentelli, "Architecture of field-programmable gate arrays," Proc. IEEE, vol. 81, no. 7, pp. 1013--1029, July 1993.

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J. Rose, A.E. Gamal, and A. Sangiovanni-Vincentelli. Architecture of FieldProgrammable Gate Arrays. Proceedings of the IEEE, July 1993. 81(7): pp. 10131029.

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J. Rose, A. El Gamal, and A. Sangiovanni-Vincentelli, "Architecture of Field - Programmable Gate Arrays," Proceedings of the IEEE, July 1993, pp. 1013-1029.

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J. Rose, A. E. Gamal, and A. Sangiovanni-Vincentelli, "Architecture of field-programmable gate arrays," Proceedings of the IEEE 81(7), pp. 1013--1029, 1993.

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