A. DeHon, "Reconfigurable architectures for general-purpose computing", Ph.D. dissertation, Massachusetts Institute of Technology, 1996. Home/Search Document Details and Download
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Using Design-Level Scan to Improve Design.. - Wheeler, Graham.. (2001) (Correct)
....is much greater than the 5 30 overheads for VLSI mentioned earl ier in this section. So why does scan cost so much more in FPG s than it does in VLSI The answerl]8 in the granul rity of the devices used for impl]6E ting scan l ogic transistorl ogic costs muchl ess than FPG LUTl ogic [7]. For exampl e, 15]cl aims that a D flip flop instrumented for scan is onl y 10 l arger in area. In an FPG design, however, instrumenting a FF for scan e#ectivel doubl6 its size, since the FF and the scan mux are each ha of an LE. The size may even tripl or quadrupl by using additional ....
A. DeHon. Reconfigurable Architectures for General-Purpose Computing.PhD thesis, Massachusetts Institute of Technology, September 1996.
Incremental Compilation for Parallel Logic Verification Systems - Tessier, Jana (2002) (Correct)
....benchmarks are summarized in Table II. Sources for the benchmarks include the RAW [24] and Prep benchmark suites [25] Subsequently, each benchmark is described along with a discussion of how the initial design was modified. Many of these modified benchmarks benefit from hardware specialization [26], the capability to directly customize a specific piece of hardware to perform a certain task. In several cases, the benchmark is specialized based on the value of constant parameters to reflect an optimization that can be integrated into the hardware. DES is an established encryption standard ....
A. Dehon, "Reconfigurable architectures for general purpose computing, " Ph.D. dissertation, Dept. of Electrical Engineering and Computer Science, Massachusetts Inst. of Technology, 1996.
A Co-simulation Study of Adaptive EPIC Computing - Valentin Stefan Gheorghita (2002) (Correct)
....PAM [24] and SPLASH 2 [9] are some pioneering efforts in this direction. More recently, researchers have explored variations of FPGA architectures and also some radical architectures, which combine programmable processor with reconfigurable logic. Some examples of the former are DPGA and MATRIX [5]; while RAW [23] PipeRerich [10] Garp [13] PRISC [18] RaPiD [6] Cameron [11] and Chimaera [12] exemplify the latter. A survey of some of the past work can be found in one of the author s thesis [20] In the last two three years, even some FPGA manufacturers have shown interest in combining ....
A. DeHon. Reconfigurable Architectures for General Purpose Computing. PhD thesis, MIT AI Lab, September 1996.
Metrics for Design Space Exploration of.. - Sciuto, Salice.. (2002) (2 citations) (Correct)
....executor classes (i.e. GPP, DSP, ASIC FPGA) An affinity of 1 towards an executor class indicates a perfect matching, while a 0 affinity indicates no matching at all. With respect to previous attempts to perform similar analysis, the proposed one is more general and accurate. For example, in [7] the efficiency of GPPs and FPGAs is evaluated only with respect to the exploitation of the available area evaluating the spatial efficiency of a device. In [9] the authors create a methodology that fully characterizes any algorithm with respect to the elements of its structure that affect its ....
A. De Hon. Reconfigurable Architectures for General-Purpose computing. Technical Report 1586, MIT-AI Laboratoty, 1996.
Reconfigurable Computing Systems - Bondalapati, Prasanna (2002) (6 citations) (Correct)
....is achieved at the cost of reconfiguration cost. Reconfigurable logic has to stop computation for initiating a new configuration. This reconfiguration time can be significant, especially for finegrain multi million gate FPGAs. Some architectures support partial and dynamic reconfiguration [10] [12], 13] 14] 15] 16] Partial reconfiguration permits reconfiguration of the functionality of a portion the device while the remaining portion retains its functionality. Dynamic reconfiguration permits reconfiguration of a portion of the device while other portions of the device are performing ....
A. DeHon, Reconfigurable Architectures for General Purpose Computing, Ph.D. thesis, MIT AI Lab, September 1996.
Fast Place and Route Approaches for FPGAs - Tessier (1999) (1 citation) (Correct)
....accomodate additional required device bandwidth. 2. CAD tool designers could reduce design bandwidth inside FPGA devices by assigning multiple design nets to the same physical routing resources inside the device and scheduling communication on the resources at statically determined times. Dehon [21] has indicated that currently about 90 of silicon area in FPGAs is devoted to routing resources. Given this observation, it would appear that the first of the two choices above may not be the best one to follow. Thus, in addition to the floorplanning and routing approaches discussed in this ....
....designs, coarser grained sub arrays will be needed. Hardware Support for Scheduled Communication As mentioned earlier, a fundamental issue affecting place and route time for any FPGA architecture is the growth rate of inter macro interconnect due to Rent s Rule limitations. As shown in [21], hierarchical interconnect structures are particularly limited by wire growth due to a high density switching bottleneck at each tree node. To reduce this bandwidth, scheduled communication between macros becomes a necessity. In general, using look up tables and flip flops in technology native to ....
A. Dehon. Reconfigurable Architectures for General-Purpose Computing. PhD thesis, Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 1996.
Fast Place and Route Approaches for FPGAs - Tessier (1998) (1 citation) (Correct)
....accomodate additional required device bandwidth. 2. CAD tool designers could reduce design bandwidth inside FPGA devices by assigning multiple design nets to the same physical routing resources inside the device and scheduling communication on the resources at statically determined times. Dehon [21] has indicated that currently about 90 of silicon area in FPGAs is devoted to routing resources. Given this observation, it would appear that the first of the two choices above may not be the best one to follow. Thus, in addition to the floorplanning and routing approaches discussed in this ....
....designs, coarser grained sub arrays will be needed. Hardware Support for Scheduled Communication As mentioned earlier, a fundamental issue affecting place and route time for any FPGA architecture is the growth rate of inter macro interconnect due to Rent s Rule limitations. As shown in [21], hierarchical interconnect structures are particularly limited by wire growth due to a high density switching bottleneck at each tree node. To reduce this bandwidth, scheduled communication between macros becomes a necessity. In general, using look up tables and flip flops in technology native to ....
A. Dehon. Reconfigurable Architectures for General-Purpose Computing. PhD thesis, Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 1996.
Modeling and Mapping for Dynamically Reconfigurable Hybrid.. - Bondalapati (2001) (2 citations) (Correct)
....Memory Memory Memory Memory D Multi FPGA Board Logic Block FF FPGA 4 LUT Figure 2. 1: Typical FPGA Board, Device and Logic block architecture 20 Current and future generation reconfigurable devices ameliorate the reconfiguration cost by providing partial and dynamic reconfigurability [32, 41, 67, 70, 83]. In partial reconfiguration, it is possible to modify the configuration of a part of the device while the configuration of the remaining part is retained. In dynamic reconfiguration devices permit this partial reconfiguration even while other logic blocks are performing computations. Devices in ....
....In dynamic reconfiguration devices permit this partial reconfiguration even while other logic blocks are performing computations. Devices in which multiple contexts of the configuration of a logic block can be stored in the logic block and the context switched dynamically have also been proposed [32, 67]. Typically, the application requirements increase at a rate faster than the increase in the size of logic resources on most FPGA devices. FPGA architectures also have limits on the I O capability due to the limitation on the number of I O pins on the device. To map large applications onto ....
A. DeHon. Reconfigurable Architectures for General Purpose Computing.PhD thesis, MIT AI Lab, September 1996.
Dynamic Runtime Scheduler Support for SCORE - Chu (2000) (Correct)
....in functional density over microprocessors. At the same time, this lower memory ratio allows reconfigurable devices to deploy active capacity at a finer grained level, allowing them to realize a higher yield of their raw capacity, sometimes as much as 10x versus conventional processors ([DEHON96]) While reconfigurable devices can be used in isolation, there is also increasing interest in hybrid architectures such as DPGA ( DEHON96] and Garp ( HAUSER97] coupling reconfigurable logic (FPGAs) with a general purpose processor (RISC) This allows applications to specialize the ....
.... capacity at a finer grained level, allowing them to realize a higher yield of their raw capacity, sometimes as much as 10x versus conventional processors ( DEHON96] While reconfigurable devices can be used in isolation, there is also increasing interest in hybrid architectures such as DPGA ([DEHON96]) and Garp ( HAUSER97] coupling reconfigurable logic (FPGAs) with a general purpose processor (RISC) This allows applications to specialize the reconfigurable hardware to match application requirements while allowing operations that run inefficiently on the reconfigurable device to execute on ....
Andr DeHon. Reconfigurable Architectures for General-Purpose Computing, AI Technical Report 1586 (Ph.D. thesis), MIT Artificial Intelligence Laboratory, 545 Technology Sq., Cambridge, MA 02139, October 1996. http://www.ai.mit.edu/people/andre/phd.html 40
Active Computing Resources - The Portions Of (Correct)
....as a first line of defense against confusion. If you find us using other terms which are unfamiliar to you or used in an unfamiliar manner, please let us know so we can clear up any confusion and expand this list. N.B. The first draft of this list appeared as an appendix in Andre s thesis. [DeH96]. Unless otherwise noted, the term is used in his thesis and the terminology appendix printed there is likely to have references to the most relevant portions. see tau. see lambda. ACS Adaptable Computing Systems Term used by DARPA for the broad reconfigurable computing field. See ....
Andr'e DeHon. Reconfigurable Architectures for General-Purpose Computing. AI Technical Report 1586, MIT Artificial Intelligence Laboratory, 545 Technology Sq., Cambridge, MA 02139, October
Array-Based Architecture for Molecular Electronics - Dehon (2001) (1 citation) Self-citation (Dehon) (Correct)
....compute, and interconnect all the key elements we need to implement computations. Further, each of these structures is amenable to sparing and remapping to avoid inevitable faults in the base array. A single, monolithic memory, PLA, or crossbar would not be useful or efficient (e.g. 13] 10] [5]) but a collection of interconnected arrays allows us to both exploit logical in0 in1 in2 in3 out oxide covered FET load Vpd (static load) Touching NT NWs forming PN junctions Gnd in3 in2 in1 Rpd(Vpd) Rjunc Rjunc Rjunc Rjunc in0 Figure 4: Diode OR Arrangement Gnd Vpd ....
Andr e DeHon. Reconfigurable architectures for general-purpose computing. AI Technical Report 1586, MIT Artificial Intelligence Laboratory, 545 Technology Sq., Cambridge, MA 02139, October 1996.
Analysis of Quasi-Static Scheduling Techniques in.. - Markovski, Caspi, .. (1 citation) Self-citation (Dehon) (Correct)
....o#ine scheduling improves schedule quality, resulting in a net reduction of total execution time by 46 81 . 1. INTRODUCTION Reconfigurable computing devices such as FPGAs have demonstrated 10x 100x gains in performance and functional density over microprocessors for a variety of applications [6], yet their popular use is limited to application specific domains or serving as ASIC replacements. These uses ignore the devices programmability and limits their applicability to only a few areas in computing. Whereas microprocessor architectures have traditionally enjoyed software compatibility ....
A. DeHon. Reconfigurable Architectures for General-Purpose Computing. PhD thesis, MIT, 545 Technology Sq., Cambridge, MA 02139, September 1996.
HARP: Hard-wired Routing Pattern FPGAs - Satish Sivaswamy Gang (Correct)
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A. DeHon, "Reconfigurable architectures for general-purpose computing", Ph.D. dissertation, Massachusetts Institute of Technology, 1996.
Distributed Arithmetic FPGA Design with Online Scalable Size and.. - Danne (2004) (Correct)
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A. DeHon. Reconfigurable Architectures for General-Purpose Computing. PhD thesis, Massachusetts Institute of Technology, 1996.
Memory Management to Support Multitasking on FPGA Based Systems - Danne (2004) (Correct)
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A. DeHon. Reconfigurable Architectures for General-Purpose Computing. PhD thesis, Massachusetts Institute of Technology, 1996.
Mapping of Regular Nested Loop Programs to Coarse-grained.. - Hannig, Dutta, Teich (2004) (Correct)
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A. DeHon. Reconfigurable Architectures for GeneralPurpose Computing. Technical Report A.I. TR No. 1586, MIT AI Lab, Massachusetts, 1996.
Dynamic Reconfiguration of Distributed Arithmetic Controllers: .. - Danne, Bobda (2004) (Correct)
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A. DeHon. Reconfigurable Architectures for GeneralPurpose Computing. PhD thesis, Massachusetts Institute of Technology, 1996.
Increasing Efficiency by Partial Hardware Reconfiguration.. - Danne, Bobda, Kalte (2003) (Correct)
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A. DeHon. Reconfigurable Architectures for GeneralPurpose Computing. PhD thesis, Massachusetts Institute of Technology, 1996.
Operating Systems for FPGA Based Computers and Their Memory.. - Danne (2004) (Correct)
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DeHon, A.: Reconfigurable Architectures for General-Purpose Computing. PhD thesis. Massachusetts Institute of Technology. 1996.
Wiring Requirement and Three-Dimensional - Integration Technology For (2003) (Correct)
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A. DeHon, "Reconfigurable architectures for general-purpose computing, " Ph.D. dissertation, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, 1996.
A Co-simulation Study of Adaptive EPIC Computing - Valentin Stefan Gheorghita (Correct)
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A. DeHon. Reconfigurable Architectures for General Purpose Computing.PhD thesis, MIT AI Lab, September 1996.
Field-Programmable Custom Computing Machines - A Taxonomy - Sima, VASSILIADIS.. (2002) (Correct)
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A. DeHon. Reconfigurable Architectures for General-Purpose Computing. A. I. 1586, Massachusetts Institute of Technology, Cambridge, Massachusetts, 1996.
Field-Programmable Custom Computing Machines - A Taxonomy - Sima, VASSILIADIS.. (2002) (Correct)
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A. DeHon. Reconfigurable Architectures for General-Purpose Computing. A. I. 1586, Massachusetts Institute of Technology, Cambridge, Massachusetts, 1996.
Pel Reconstruction on FPGA-Augmented TriMedia - Sima, Cotofana, Vassiliadis.. (2004) (Correct)
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A. DeHon, "Reconfigurable architectures for general-purpose computing," in A. I. 1586. Cambridge, MA: Massachusetts Inst. Technology, 1996.
Improving Design Observability and Controllability for Functional .. - Wheeler (2001) (4 citations) (Correct)
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Andre DeHon, Reconfigurable Architectures for General-Purpose Computing, PhD thesis, Massachusetts Institute of Technology, September 1996.
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