R. Ernst, J. Henkel and Th. Benner, Hardware/Software Co-Synthesis for Microcontrollers, IEEE Design & Test of Computers, pp. 64--75, Dec. 1993.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....as discussed in section 3. We will now take a closer look at the synthesis steps. 4.1. Partitioning In the partitioning step the user annotates each activity of the top level activity chart with a thread or an interface tag. We do not automate this step. Other approaches to codesign like [8, 4] concentrate on this topic, but since startup time of threads is an important issue with our target architecture, we belief that manual partitioning at this design level will give the best results. After threads and hardware components are identified, they must be mapped to the architecture. As ....

R. Ernst, J. Henkel, and T. Benner. Hardware/software co-synthesis for microcontrollers. IEEE Design & Test of Computers, Dec. 1993.

....Coarse grain Task Graph, Dynamic Programming, Scheduling, Blocking Non blocking Communication, Mid way Communication. Processes. I. Introduction P REVIOUS work on system level synthesis has focused mainly on ne grain hardware software partitioning. Examples include VULCAN II [1] and COSYMA [2]. These programs automatically partition the input speci cation into basic blocks (or ne grain operations) and move the basic blocks to hardware or software components while satisfying the given constraints. The resulting ne grain partitioning may, however, move logically coherent blocks across ....

R. Ernst, J. Henkel, and Th. Benner, \Hardware/Software CoSynthesis for Microcontrollers," IEEE Design and Test Magazine, vol. 10, no. 4, Dec. 1993.

....within the same application system. Keywords Hardware software codesign, Communication synthesis, Protocol selection allocation, Interface generation I. INTRODUCTION Recently the synthesis community has moved toward the highest level of abstraction commonly known as the system level [4] [9] [15] 16] 20] 32] This move vas motivated by the increasing complexity of systems and by the need for a unified approach to allow the development of systems containing both hardware and software. As the level of abstraction rise some problems heretofore non existing appear [12] 38] At the ....

....as an allocation problem aimed at selecting, from a library, a set of communication units that implement the data exchange between the subsystems. B. Previous work Most of the work in communication synthesis for codesign has focussed on interface synthesis assuming a fixed network structure [9] [15] Only few works in codesign handle network synthesis [7] 13] 37] In [13] Gong s network synthesis is guided by the mapping of variables (shared or private) to memory (local or global) In [37] Yen create a new processing element and a bus when it is not possible to assign a process to an ....

R. Ernst, J. Henkel, and T. Benner, Hardware/Software CoSynthesis for Microcontrollers, IEEE Design & Test of Computers, Vol. 10 No. 4, pp. 64-75, December 1993.

....The implementation under real time constraints is an aspect usually not directly supported in OO systems. This problem has been tackled by a number of researchers, though. Systems like Adept[KAJW96] Cathedral[VLM96] Castle[Str94] Chinook[COB95] Polis[BHJ 96] Cosmos[JAB94] Cosyma[EHB93] Lycos[MGK 97] or Vulcan[GdM96] all allow specification of timing bounds to generate complete hardware and software implementations from the input specification. They focus on HW SW co design with its typical questions of partitioning, HW selection or production, SW and communication ....

R. Ernst, J. Henkel, and T. Benner. Hardware/software cosynthesis for microcontrollers. IEEE Design & Test of Computers, 10(4):64--75, December 1993.

....scheduling and allocation with partitioning is demonstrated. 1 Introduction Hardware software partitioning is often viewed as the synthesis of an architecture consisting of a single CPU and a single dedicated hardware component (full custom, FPGA, etc. from an initial system specification, e.g. [1]. The aim of this paper is to emphasize the importance of clearly defining and reporting the partitioning model assumed by a partitioning algorithm and to demonstrate the kind of errors that may occur if the results produced by a partitioning algorithm which assumes a simplistic partitioning model ....

....and prototyping [8] Further, it is the most commonly used target architecture for automatic hardware software partitioning approaches. The hardware software partitioning of a system specification onto a single CPU, single ASIC architecture has been investigated by a number of research groups [1, 2, 3, 5, 6, 9] which have employed widely different input languages (C, C x , VHDL, etc. and system models, and have had different optimization goals and constraints in mind. This makes it very difficult to compare the approaches. The different approaches will be described and discussed in section 3 and 4. ....

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R. Ernst, J. Henkel, and T. Benner. Hardware/software co-synthesis of microcontrollers. Design and Test of Computers, pages 64--75, December 1992.

....the beginning or end of their lifetime. The proposed algorithm has been implemented. Experimental results are reported and discussed. 1 Introduction Previous work on system level synthesis has focused mainly on fine grain hardware software partitioning. Examples include Vulcan II [1] and Cosyma [2]. These programs automatically partition the input specification into basic blocks (or fine grain operations) and move the basic blocks to hardware or software components while satisfying the given constraints. The resulting fine grain partitioning may, however, move logically coherent blocks ....

R. Ernst, J. Henkel, and Th. Benner. Hardware/Software Co-Synthesis for Microcontrollers. IEEE Design and Test Magazine, 10(4), December 1993.

....chip and n the number of code fragments which may be placed in either hardware or software. 1 Introduction The hardware software partitioning of a system specification onto a target architecture consisting of a single CPU and a single ASIC has been investigated by a number of research groups [2, 5, 1, 7, 8, 11]. This target architecture is relevant in many areas where the performance requirements cannot be met by generalpurpose microprocessors, and where a complete ASIC solution is too costly. Such areas may be found in DSP design, construction of embedded systems, software execution acceleration and ....

....construction of embedded systems, software execution acceleration and hardware emulation and prototyping [10] One of the major differences among partitioning approaches is in the way communication between hardware and software is taken into account during partitioning. Henkel, Ernst et al. [2, 1, 6] present a simulated annealing algorithm which moves chunks of software code (in the following called blocks) to hardware until timing constraints are met. The algorithm accounts for communication and only variables which need to be transferred are actually taken into account, i.e. the ....

R. Ernst, J. Henkel, and T. Benner. Hardware /software co-synthesis of microcontrollers. Design and Test of Computers, pages 64--75, December 1992.

....implementation of the interface between client server modules, termed interface synthesis. The main motivation is to adapt the interface during system implementation, rather than having a fixed communication architecture as is the case in most hardware software codesign approaches, e.g. [2, 5, 6] which are using memory mapped I O. The simplest system consists of a single client invoking one operation from a server, i.e. a point to point communication. This corresponds to the traditional view of hardware software codesign where we initially have an application which can not fulfill some ....

R. Ernst, J. Henkel, and T. Benner. Hardware/software cosynthesis for microcontrollers. IEEE Design & Test of Computers, pages 64--75, December 1993.

....partitioning, analysis, estimation 1. Introduction Hardware software partitioning is often viewed as the synthesis of a target architecture consisting of a single CPU and a single dedicated hardware component (full custom, FPGA, etc. from an initial system specification, e.g. as in [15]. The partitioning onto such a target architecture is depicted in figure 1. Even though the single CPU, single ASIC architecture is a special and limited example of a distributed system, the architecture is relevant in many areas such as DSP design, construction of embedded systems, software ....

....summary and some directions for on going and future work. 4 2. Related Work Several research groups have addressed the problem of co synthesis and in particular that of hardware software partitioning. The field of hardware software partitioning was pioneered by two research groups; COSYMA [14] [15], 27] by Ernst et al. and Vulcan [21] 22] by Gupta and De Micheli. The COSYMA system performs hardware software partitioning on an internal representation which is an extended syntax graph. This representation is used for initial analysis such as simulation and profiling. The representation is ....

R. Ernst, J. Henkel, and T. Benner. Hardware/software co-synthesis of microcontrollers. Design and Test of Computers, pages 64--75, December 1992.

....Section 5 concludes this paper. At this point we will also discuss our experience with STATEMATE as programming environment for prototyping oriented HW SW codesign projects. Related Work. Many approaches on hardware software codesign concentrate on the hardware software partitioning problem [17, 10, 14, 27, 1, 20]. In these approaches, time critical components are automatically identified and implemented in hardware. But in contrast to EVENTS, these approaches are not designed to support prototyping. Graphical specification languages are used in several environments. The PTOLEMY [19, 5] framework uses ....

....all activities are computed and stored as VHDL alike entities in the project database. HW SW Partitioning. In the partitioning step, the user annotates each activity of the top level activity chart with an hardware or software tag. We do not automate this step. Other approaches to codesign like [14, 10, 20] concentrate on this topic, but we believe that for prototyping manual partitioning is more appropriate. Interface analysis. The interface analysis step is used twice in the code generation process. In the first stage, we determine the dataflow between components. The result of this stage is used ....

R. Ernst, J. Henkel, and T. Benner. Hardware/software co-synthesis for microcontrollers. IEEE Design & Test of Computers, Dec. 1993.

....The HW SW prototyping system consists of a SPARC processor, an FPGA based coprocessor with HW SW debugging features realized with a high speed microcontroller. 1 Introduction COSYMA (CoSYnthesis of embedded Micro Architectures) is one of the first systems for hardware software cosynthesis [1]. It is targeted to the design of small embedded controllers. Given an input description in a superset of C, C x , consisting of one or more tasks with time constraints, and given a fixed core processor, COSYMA tries to map as much of the system as possible to software. When the time constraints ....

R. Ernst, J. Henkel and Th. Benner, Hardware/Software Co-Synthesis for Microcontrollers, IEEE Design & Test of Computers, pp. 64--75, Dec. 1993.

....changes in the system descriptions or adaptation to special user requirements. Only those parts for which a software realization could not meet the timing requirements should be executed in application specific hardware. This was also intended as a pilot project for the co synthesis system COSYMA [3]. The target system was defined to be a single board processor co processor system, which could be configured to run one of the applications at a time. Since the project was planned as a case study, we decided to realize the coprocessor as an FPGA prototype. For the FPGA solution the real time ....

R. Ernst, J. Henkel, and T. Benner. Hardware/software cosynthesis for microcontrollers. IEEE Design & Test of Computers, 10(4):64--75, Dec. 1993.

....techniques are compared. The first technique uses a pico kernel. The second technique is based on code motion and merging (CMM) The latter technique derives a finite state machine from the control flow of the original program. For the investigations, we use the cosynthesis system COSYMA [7]. The COSYMA input description consists of a functional description in C X , which is basically C with parallel processes, and a control file. All process communication in C X is point to point via logical channels with no global variables. The control file defines the mapping of logical to ....

R. Ernst, J. Henkel and Th. Benner, Hardware/Software Co-Synthesis for Microcontrollers, IEEE Design & Test of Computers, pp. 64--75, Dec. 1993.

....due to synthesis, compiler and communication effects. This paper describes an approach to adapt the estimation. The results show fast convergence of estimated to real costs. 1 Introduction The system COSYMA (COSYnthesis of eMbedded Architectures) has been described in earlier publications (e.g. [ErHeBe93]) So far hardware software partitioning in COSYMA was based on estimated results only. This has lead to suboptimal results. This paper presents the adaptation of the estimation to actual values in an outer partitioning loop. In this section a summary of COSYMA is given. Section 2 describes a ....

....and is based on profiling data. For the sake of fast turnaround times these values are estimated and the cost function is updated in each step of the annealing algorithm. This iterative partitioning based on estimation is called inner partitioning loop and has already been described in detail in [ErHeBe93]. After partitioning those parts which have been selected to be realized in software are translated to a Cprogram thereby inserting code for the communication with the co processor. The rest is translated to the input description of the high level synthesis system BSS (see [Ho93] also ....

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R. Ernst, J. Henkel and Th. Benner, Hardware/Software Co-Synthesis for Microcontrollers, IEEE Design & Test of Computers, pp. 64--75, Dec. 1993.

....an all software solution) decides about the HW SW tradeoff using a binary search algorithm. The approach described in [KaLe94] uses an algorithm called GCLP that takes into consideration a global time critical measure and a set of local criteria in order to determine the HW SW tradeoff. COSYMA [ErHeBe93] also belongs to the class of software oriented approaches and uses the simulated annealing algorithm for automating the HW SW partitioning process. Other approaches [BaRoXi94] JaElOb 94] also focus on HW SW partitioning but still need some user interaction. All these approaches have in common ....

....time and on trace data. The path based estimation technique presented in this paper provides the hardware runtime estimation. After partitioning, hardware and software synthesis are executed and the actual values for hardware runtime, chip area, are fed back. For more details on COSYMA see [ErHeBe93]. If the constraints (CS) have not been met, the whole procedure is repeated. Reason for a deviation from the given constraints is that estimation cannot predict all local and global optimization effects in the computation intensive hardware and software synthesis processes. As shown in figure 2, ....

R. Ernst, J. Henkel and Th. Benner, Hardware /Software Co-Synthesis for Microcontrollers, IEEE Design & Test Magazine, Vol. 10, No. 4, Dec. 1993.

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R. Ernst, J. Henkel and T. Benner, Hardware/Software Co-Synthesis for Microcontrollers, IEEE Design & Test of Computers, Vol. 10 No. 4, pp. 64-75, December 1993.

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