J. Alvarez, H. Sanchez, G. Gerosa, and R. Countryman, "A Wide-Bandwidth Low-Voltage PLL for PowerPC Microprocessors," IEEE Journal on Solid-State Circuits, vol. 30, pp. 383--391, April 1995. 29  Home/Search   Document Not in Database   Summary   Related Articles   Check

....latency from the processor, respectively. 3. 2 Estimating the Energy Consumed To estimate the energy consumed in the chip, we have applied scaling down theory to data on existing devices reported in the literature, as well as used several techniques and formulas reported in the literature [25, 26, 27, 13, 28, 29]. A detailed discussion of the methods that we have followed can be found in [20] In this section, we give an overview of how we estimate the energy consumed in the processor cores, memory hierarchies, and clocks. We also discuss how we validated the models. Processor Cores Each core is a ....

....The clock network is laid out in the chip using an H tree structure to minimize skew. To estimate the overall energy of the clocking system, we estimate and add the contributions of several components, namely PLL, DLLs, buffers, and distribution lines. Such contributions are estimated based on [25] and on capacitance models. Overall, the estimated average energy per cycle is 957.5 pJ. This figure does not include the energy for the clock inside the processor cores. The latter is included in the computation for the cores. Further details can be found in [20] Validation We validate our ....

J. Alvarez, H. Sanchez, G. Gerosa, and R. Countryman, "A Wide-Bandwidth Low-Voltage PLL for PowerPC Microprocessors," IEEE Journal on Solid-State Circuits, vol. 30, pp. 383--391, April 1995. 29

....output clock period can be a fraction of the reference clock period if a frequency divider is implemented in the loop feedback path. This frequency multiplication property is the main reason for the widespread adoption of PLL s in applications such as microprocessor clock generation [56] 57] [58]. Moreover, since the VCO inherently generates a periodic clock signal, PLL s utilizing appropriate phase detector designs are commonly used in clock and data recovery applications [59] Delay locked loops on the other hand, make use of the fact that in many applications the reference clock ....

J. Alvarez, et al. "A wide-bandwidth low-voltage PLL for PowerPC microprocessors, " IEEE Journal of Solid-State Circuits, April 1995. vol.30, no.4, pp. 383-91.

....for the overhead of the execution in the OS. 3. 2 Estimating the Energy Consumed To estimate the energy consumed in the chip, we have applied scaling down theory to data on existing devices reported in the literature, as well as used several techniques and formulas reported in the literature [3, 30, 18, 24, 34, 35]. A detailed discussion of the methods that we have followed can be found in [36] In this section, we give an overview of how we estimate the energy consumed in the processor cores, memory hierarchies, and clocks. We also discuss how we validated the models. 6 Processor Cores Each core is a ....

....The clock network is laid out in the chip using an H tree structure to minimize skew. To estimate the overall energy of the clocking system, we estimate and add the contributions of several components, namely PLL, DLLs, buffers, and distribution lines. Such contributions are estimated based on [3] and on capacitance models. Overall, the estimated average energy per cycle is 957.5 pJ. This figure does not include the energy for the clock inside the processor cores. The latter is included in the computation for the cores. Further details can be found in [36] Validation We validate our ....

J. Alvarez et al. A Wide-Bandwidth Low-Voltage PLL for PowerPC Microprocessors. IEEE Journal on Solid-State Circuits, 30(4):383-- 391, April 1995.

....pJ, while for the other, simpler instructions, the value is 81 pJ. Recall that the processor is simple and that its 28 16 bit instructions are optimized for intelligent memory operation [24] The energy consumed by the clock in the whole chip is estimated to be 907 pJ per cycle assuming 1 main PLL [6] and 16 distributed local DLLs [38] with meshed clock signal routing [24] The calculation is performed for 800 MHz and 1.8 V and extended for di erent voltage and frequency as required by schemes described in Chapter 4. The energy required for di erent cache operations is shown in Table 5.4. ....

J. Alvarez et al. A wide-bandwidth low-voltage pll for powerpc microprocessors. IEEE J. of Solid-state Circuits, 30(4):383-391, April 1995.

....the output clock period can be a fraction of the reference clock period, if a frequency divider is implemented in the loop feedback path. This frequency multiplication property is the main reason for the widespread adoption of PLL s in applications such as microprocessor clock generation [20] 21] [22]. Moreover, since the VCO inherently generates a periodic clock signal, PLL s utilizing appropriate phase detector designs are commonly used in clock and data recovery applications [23] Delay Locked Loops on the other hand, make use of the fact that in many applications the reference signal is ....

Alvarez, J. et al. "A wide-bandwidth low-voltage PLL for PowerPC microprocessors" IEEE Journal of Solid-State Circuits, April 1995. vol.30, no.4, p. 383-91

....chips may become unreliable at high temperatures. Consequently, many techniques have been proposed and implemented to limit the temperature of a chip, to use energy in chips more eciently, or both. These techniques range from the transistor and logic levels [41] up to the architectural level [2, 5, 6, 8, 11, 12, 13, 18, 19, 20, 21, 24, 25, 33, 43, 46, 1 49]. To address these issues, recent processors are including support for low power operation [13, 18] This support largely consists of reducing voltage and frequency [13, 18] or various sleep modes. In general, however, most of the proposed low power techniques have been proposed to work ....

.... Among others, they include putting the whole or part of the system in sleeping mode [19, 20, 43] reducing the voltage and or frequency [8, 13, 18] gating pipeline signals, for example to control speculative instructions [6, 33] clock optimizations, including multiple clocks and clock gating [2, 12]; better signal encoding [5, 12] low power memory design techniques [21] like bank partitioning or divided word line; low power cache design techniques like cache block bu ering [49] sub banking [11, 46] lter caches [24] or instruction cache throttling [43] and TLB optimizations [25] In ....

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J. Alvarez et al. A Wide-Bandwidth Low-Voltage PLL for PowerPC Microprocessors. IEEE J. of Solid-state Circuits, 30(4):383-391, April 1995.

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J. Alvarez, et al., "A wide-bandwidth low-voltage PLL for PowerPC microprocessors," IEEE Journal of Solid-State Circuits, Apr. 1995, vol.30, no.4,

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