H. Touati, H. Savoj, B. Lin, R. K. Brayton, and A. Sangiovanni-Vincentelli. Implicit state enumeration of finite state machines using BDD's. In ICCAD90 Home/Search Document Not in Database Summary Related Articles Check |
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Hardware-Software Covalidation: Fault Models and Test Generation - Harris (Correct)
....the complexity of the test generation process. Binary Decision Diagrams (BDDs) have been used to represent the state transition relation and efficiently perform implicit state enumeration by defining an image computation which computes the states which are reachable from a given set of states [52]. The efficiency of this method of state enumeration has led to its use during the state machine test generation process [26, 34] BDDs are also used at the behavioral level to describe the CDFG of a behavioral VHDL description [53, 39, 54] In these approaches, the functions implemented by each ....
H. J. Touati, H. Savoj, B. Lin, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Implicit state enumeration of finite state machines using bdd's", in International Conference on Computer-Aided Design, pp. 130--133, November 1990.
Efficient Verification with BDDs using Implicitly Conjoined.. - Hu, Dill (1993) (13 citations) (Correct)
....its application. 1 Introduction With the increasing cost and complexity of hardware designs and protocols, formal verification techniques become ever more attractive. Boolean decision diagrams (BDDs) 3] have enabled much progress in this area, from the early work applying BDDs to verification [1, 6, 5, 8, 19] through the current work of numerous researchers. Most of the current research on automatic formal hardware verification has focused on gate and transistor level design. We believe that automatic formal verification also has an important role at the very high level of design, for example, in ....
....leading to a state not in I, and, if there is such a path, to output that path as a counterexample to the property being verified. The usual approach to such a verification task is to compute the set of states reachable from S and to check that the set of reachable states is a subset of I (e.g. [8, 5, 7, 19, 4]) This approach entails computing the set of reachable states as the fixed point Z:u:S(u) 9v[Z(v) ffi (v; u) which is the smallest set Z such that S Z and any state that is a successor under ffi of a state in Z is also in Z [6] We will call this approach forward traversal. The ....
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Herve J. Touati, Hamid Savoj, Bill Lin, Robert K. Brayton, and Alberto SangiovanniVincentelli, "Implicit State Enumeration of Finite State Machines using BDD's" IEEE International Conference on Computer-Aided Design, 1990, pp. 130--133.
New Techniques for Efficient Verification with Implicitly.. - Hu, York, Dill (1994) (11 citations) (Correct)
....verification is attracting increasing interest as a tool to deal with the ever increasing cost and complexity of hardware designs and protocols. Binary decision diagrams (BDDs) 3] have enabled much of the recent progress in this area, starting from the early work applying BDDs to verification [1, 6, 5, 11, 24] and continuing through the current work of many researchers. Current research on automatic formal hardware verification has focussed mainly on gate and transistor level design. We believe that automatic formal verification also has an important role at the very highest levels of design, for ....
....reach a state in Z , and BackImage gives the set of states that in one transition must end up in Z . These image operators form the basic operations of BDD based verification algorithms. If Z and ffi are both represented by small BDDs, these operations can be done directly using BDD operations [6, 5, 24]. If the BDD for ffi is too large to build (a common problem) a number of techniques are available to compute these images without building the BDD for ffi [4, 18] Also, note that BackImage(ffi; Z) PreImage(ffi; Z) so if Z is represented by a small BDD, computing either of these two images ....
[Article contains additional citation context not shown here]
Herve J. Touati, Hamid Savoj, Bill Lin, Robert K. Brayton, and Alberto Sangiovanni-Vincentelli, "Implicit State Enumeration of Finite State Machines using BDD's" IEEE InternationalConferenceon Computer-Aided Design, 1990, pp. 130--133. 7
Efficient Model Checking by Automated Ordering of Transition .. - Daniel Geist Ilan (1994) (36 citations) (Correct)
....a BDD of its transition relation. The size of the BDD of the transition relation is usually the obstacle to verifying bigger circuit designs. Recent research has shown that it is possible to significantly reduce the amount of space required by the transition relation, if it is not kept as a whole [5, 7, 12]. The space required by the transition relation can be much smaller if it is partitioned into many small relations whose combination produces the transition relation. This partition usually increases computation time but allows the verification of bigger circuit designs. Specifically, in a recent ....
H. J. Touati, H. Savoj, B. Lin, R. K. Brayton, and A. Sangiovanni-Vincentelli. Implicit State Enumeration of Finite State Machines usin BDD's. In IEEE International Conference on CAD, pages 130--133, 1990. 9
Compositional Reasoning in Model Checking - Berezin, Campos, Clarke (1998) (16 citations) (Correct)
....Reasoning in Model Checking Sergey Berezin 1 S ergio Campos 2 Edmund M. Clarke 1 1 Carnegie Mellon University USA 2 Universidade Federal de Minas Gerais Brasil [ January 23, 1998 ] Abstract. This is our abstract. And this is the Brayton s paper reference: [18]. 1 Introduction Symbolic model checking is a method for verifying complex finite state reactive systems [4] It models a computer system as a state transition graph. Efficient algorithms are used to traverse this graph and determine whether various properties are satisfied by the model. By ....
H. J. Touati, H. Savoj, B. Lin, R. K. Bryton, and A. Sangiovanni-Vincentelli. Implicit state enumeration of finite state machines using bdd's. In IEEE Int. Conf. Computer-Aided Design, pages 130--133, 1990.
Improving the Reachability Analysis Technique by Circuit Retiming - Min Zhou Yuji (Correct)
....domain of a given boolean function and of the inverse image of a subset of the codomain of a function. Coudert et al. C89] first proposed an efficient recursive method using a breadth first traversal technique. Their algorithm is based on formal manipulations of boolean functions. Touati et al. [T90] improved this implicit reachability analysis using the breadth first traversal by an efficient unified state enumeration algorithm which is based on transition relations. It turned out that Touati s technique outperforms Coudert s algorithm in most practical cases. These BDD based implicit ....
H.J. Touati, H. Savoj, B. Lin, R.K. Brayton, and A. Sangiovanni-Vincentelli, "Implicit State Enumeration of Finite State Machines using BDDs", IEEE International Conference on Computer-Aided Design, 1990.
Boolean Function Representation Based on Disjoint-Support.. - Bertacco, Damiani (Correct)
....hardware verification. 1 Introduction Reduced, Ordered Binary Decision Diagrams (ROBDDs) 1] are probably the most powerful data structure known so far for the manipulation of large logic functions, and for this reason they have become pervasive in logic synthesis and verification environments [2, 3, 4, 5]. Ongoing research is attempting to extend their applicability to other domains, such as word level verification [6] the solution of graph problems and integer linear programming [7, 8] Still, some key inefficiencies (an exponential blowup for some classes of functions, the unpredictability of ....
H. Touati, H. Savoj, B. Lin, R.K. Brayton, and A. Sangiovanni-Vincentelli. Implicit state enumeration of finite state machines using BDD's. In Proc. ICCAD, pages 130--133, November 1990.
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H. Touati, J. Savoj, B. Lin, R. Brayton, and A Sangiovanni-Vincentelli. Implicit state enumeration of finite state machines using bdds. International Conference on Computer Aided Design, 1991.
Synthesis of Hazard-Free Multilevel Logic Under Multiple-Input .. - Lin, Devadas (1995) (4 citations) Self-citation (Lin) (Correct)
....in the case of an incompletely specified function, the don tcare minterms contained inside some specified transition t 2 T must be assigned properly so that no functional hazards can occur. The other don t care minterms can be used for optimization, for example using techniques described in [9, 24] (cf. the restrict and the generalized cofactor operators) So for all practical purposes, we only need to consider completely specified functions. Once this preprocessing step is performed, the synthesis procedure is as follows: 1. Construct a BDD G for the Boolean function f . The BDD here is ....
H. J. Touati, H. Savoj, B. Lin, R. K. Brayton, and A. Sangiovanni-Vincentelli. Implicit state enumeration of finite state machines using BDD's. In ICCAD-90, pages 130--133, November 1990.
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H. Touati, H. Savoj, B. Lin, R. K. Brayton, and A. Sangiovanni-Vincentelli. Implicit state enumeration of finite state machines using BDD's. In ICCAD90
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H. J. Touati, H. Savoj, B. Lin, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Implicit state enumeration for finite state machines using BDD's," in Digest of Technical Papers of the IEEE International Conference on Computer-Aided Design, pp. 130--133, November 1990.
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H. Touati, H. Savoj, B. Lin, R. Brayton, and A. Sangiovanni-Vincentelli. Implicit State Enumeration of Finite State Machines using BDD's. In Proceedings of the International Conference on Computer-Aided Design, pages 130--133, November 1990.
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H. J. Touati, H. Savoj, B. Lin, R. K. Brayton, and A. SangiovanniVincentelli. Implicit state enumeration of finite state machines using BDDs. In International Conference on Computer-Aided Design, 1990.
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H. J. Touati, H. Savoj, B. Lin, R. K. Brayton, and A. Sangiovanni-Vincentelli. Implicit State Enumeration of Finite State Machines Using BDDs. In Proceedings of the IEEE International Conference on Computer-Aided Design(ICCAD'90), pages 130--133, 1990.
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H.J. Touati, H. Savoj, B. Lin, R.K. Brayton, and A. Sangiovanni-Vincentelli. Implicit state enumeration of finite-state machines using BDDs. In Proc. of ICCAD 90: Computer-Aided Design, pages 130--133. IEEE Computer Society Press, 1990. 13
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H. J. Touati, H. Savoj, B. Lin, R. K. Brayton, and A. Sangiovanni-Vincentelli. Implicit State Enumeration of Finite State Machines Using BDDs. In Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD'90), pages 130--133, Santa Clara, CA, Nov. 1990.
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H. J. Touati, H. Savoj, B. Lin, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Implicit state enumeration of finite state machines using BDD's", in International Conference on Computer-Aided Design, pp. 130--133, November 1990.
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H.J. Touati, H. Savoj, B. Lin, and A. Sangiovanni-Vincentelli. Implicit state enumeration of finite state machines using BDDs. In International Conf. on Computer Aided Design, 1990.
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H. J. Touati, H. Savoj, B. Lin, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Implicit state enumeration of finite state machines using BDD's," in Proc. Int. Conf. Computer-Aided Design, 1990, pp. 130--133.
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H. J. Touati, et al., "Implicit State Enumeration of Finite State Machines using BDD's," Proc. Int. Conf. Computer-Aided Design, pp.130-133, San Jose, USA, Nov. 1990.
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