J. Ousterhout, G. Hamachi, R. Mayo, W. Scott, and G. Taylor, "Magic: A VLSI layout system," in Proc. 21st Design Automaton Conf., June 1984.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....other paths are similar to those described above. 5.3 Layout We performed our tests on a 4 x 12 version of the multiplier design. We chose 4x 12 because it offers a deep pipeline (36 stages of computation) while keeping simulation time and memory usage reasonable. We used the layout editor Magic [8] to create a physical layout of our design. The layout is 0.7 mm x 1.8 mm. We emphasized ease of design; thus, in many regions the layout is Figure 13. The False Side of a Dual Rail SelfResetting Domino AND Gate Supply Induct. Current Noise Ampi. Logic 1 nH 286 mA 76 mV Preswitching 3 nH 33 mA ....

J. K. Ousterhour, G. T. Hamachi, et al. Magic: A VLSI layout system. In Proceedings of the 21th ACM/IEEE DAC, pages 152 159, Albequerque, NM, June 1984.

....low power consumption. We use the wolfe tool within OCT [8] to do the placement and routing. Wolfe in turn calls TimberWolfSC 4.2 [9] to do the placement and global routing, and YACR [10] to do the detailed routing. For the PLA layout style, we flatten the examples, and then generate the magic [11] layout for the resulting PLA using a perl script. To compute the delay, we simulate a maximally loaded output line pulled down by a single output pull down device. Parasitics from Table 1 were utilized to model the interconnect within a PLA. The results of this comparison are listed in Table 2. ....

G. T. Hamachi, R. N. Mayo, and J. K. Ousterhout, "Magic: A VLSI Layout system," in 21st Design Automation Conference Proceedings, 1984.

....a big penalty of usage. It would seem that since the routing grid has twice the pitch of the traditional grid, our routes would take 4 times the area of designs routed using existing routing methodologies. We first created a group of 14 static CMOS cells in our layout methodology, using the MAGIC [12] layout editor. We will henceforth refer to these as fabric cells . These cells followed the gridding conventions described in this paper, and did not use Metal2 at all. The transistor level design of these cells matched that of a control set of 14 standard cells that were part of an existing ....

G. T. Hamachi, R. N. Mayo, and J. K. Ousterhout, "Magic: A VLSI Layout system, " in 21st Design Automation Conference Proceedings, 1984.

....2:1 timing y f Figure 5: Transmitter channel these two approaches to design. The entire chip was designed by the author; accordingly, the level of design skill is comparable for both the synchronous and asynchronous portions. Furthermore, both parts were designed using the same tools (magic [12], CAzM [4] irsim [14] and Synchronized Transitions [17] and with the same criteria: to be fast and simple. On the other hand, the STARI chip performs little actual computation. This means that pipelining and handshaking overhead figure prominently in the comparison. In the context of the STARI ....

John K. Ousterhout, Gordon T. Hamachi, et al. Magic: A VLSI layout system. In Proceedings of the 27th ACM/IEEE Design Automation Conference, pages 152--159, Albequerque, NM, June 1984.

....to store geometry in a database. The list of early interactive VLSI layout editors include Caesar [Ousterhout, 1981] Cabbage [Hseuh, 1979] KIC2 [Keller and Newton, 1982] and others [Kedem, 1982] Bentley and Friedman, 1979] This period of research culminated with the Magic Layout System [Ousterhout et al. 1984] which has since been the mainstay of academic VLSI layout editors. In fact, our test implementation was built upon Magic since it was best available layout editor with source code available. In conclusion, the current experience of viewing a large layout with existing layout systems is becoming ....

....Section 2.1.5, while it would be possible to view these designs using a pure clipmap solution, the tremendous memory cost makes it unattractive. The size of the designs that we chose as examples was limited primarily by the memory footprint of the Magic layout system. Magic uses a Corner stitched [Ousterhout, 1984] data structure to hold the layout information which explicitly maintains a record of the empty space between rectangles so that an entire plane of rectangles resembles a quilt made up of what Magic calls tiles. This data structure is an extremely compute efficient way to store rectangles for ....

John Ousterhout, G.T. Hamachi, R.N. Mayo, W.S Scott, and G.S. Taylor. Magic: A VLSI Layout System. In 21st Design Automation Conference Proceedings, pages 152--159, June 1984.

....the layout may become fuzzy because the necessary texture tiles have not yet been created. As the viewpoint remains constant, and the necessary tiles are created, the image refines itself. 9. IMPLEMENTATION AND RESULTS The system described was implemented by modifying the Magic Layout System [5]. The OpenGL [3] graphics library was used to render the designs. For the rest of the the paper, this implementation will be called glLayoutView. Experiments were run to compare the performance of glLayoutView, the Magic Layout System (version 6.5a) and two popular commercial tools, A and B. ....

J. Ousterhout et al., "Magic: A VLSI Layout System," 21st Design Automation Conference, 1984, pp. 152--159.

....represent empty space. For example, quadtrees and octrees [13] provide 2D and 3D discrete approximations of full and empty space using a hierarchy of axis aligned cells. Corner stitching [11] the exact space representation for axis aligned rectangles used in the MAGIC VLSI layout system [12], supports efficient queries of full and empty spaces adjacent to a given full or empty space. However, the basic structure of the cornerstitching algorithm tiles the plane with full space and empty space rectangles, without supporting overlapping rectangles. Overlapping full space rectangles have ....

Ousterhout, J., Hamachi, G., Mayo, R., Scott, W., and Taylor, G. The Magic VLSI Layout System. IEEE Design & Test of Computers, 2 (1), February 1985, 19--30.

....fast in answering maze expansion related queries. The efficiency of our point to point gridless routing engine is validated when we apply it to the incremental routing problem in [74] called the ECO problem in that paper) It was compared with the explicit uniform grid based approach and Iroute [75, 76], a well known tile based router for gridless routing, The results show that the implicit representation of the NUG graph is very efficient in memory usage, smaller than that of the explicit representation and 2 to 3 smaller than Iroute. The queries supported by our data structure are also very ....

J. Ousterhout, G. Hamachi, R. Mayo, W. Scott, and G. Taylor, "Magic: A VLSI layout system," in Proc. 21st Design Automaton Conference, pp. 152--159, Jun 1984.

....and all of the instructions using that physical register have completed or have been discarded, that physical register can again be added to the free list. We have generated layout for the timing critical functions of the register renaming unit. This layout 2 was created by hand in Magic [6] and verified in HSPICE [4] Issue widths of 1, 2, 4, and 8 have been considered. The following subsections present details about our implementation. 2.1. Register alias table The RAT hardware was implemented as a specialized SRAM memory. It consists of sense amp and decode hardware along with ....

J. K. Osterhout, G. T. Hamachi, R. N. Mayo, W. S. Scott, and G. S. Taylor. Magic: A VLSI layout system. In Proc. 21st Design Automation Conf., pages 152--159. ACM/IEEE, 1984.

....are inserted We begin by briefly reviewing the corner stitching data structure and its variations. Corner stitching is a data structuring technique proposed by Ousterhout [1] for representing rectangular tiles in interactive VLSI layout editing systems and was used to implement the Magic system [3]. It allows fast, localized algorithms for a variety of interactive and batch operations [1] Corner stitching was subsequently extended to trapezoidal tiles by Marple et al. and was used to implement the Tailor system [4] Corner stitching was later extended to curved tiles by S equin and Facanha ....

J. Ousterhout, G. Hamachi, R. Mayo, W. Scott, G. Taylor, "Magic: A VLSI layout system," in Proc. of 21st Design Automation Conf., pp. 152--159, 1984.

....using segments is presented in [20] Zheng, etc. al. presented an implicit representation of the routing graph, that is, their graph nodes are computed on the fly [56] The underlying graph in their approach is an extension to the track graph introduced in Ex. Uniform Non Uniform Grid Iroute [1, 40] Expl. Runtime Impl. Runtime Mem (MB) sec. MB) sec. MB) eco 1 160.2 19.1 10.9 42.15 32.7 eco 2 160.2 6.3 10.9 26.58 32.7 eco 3 160.2 34.5 7.2 68.70 32.6 eco 4 161.7 24.0 10.9 57.39 32.6 eco 5 191.0 12.3 12.7 43.14 35.2 eco 6 359.4 24.7 15.9 74.29 52.6 eco 7 641.1 38.2 43.6 79.79 84.7 ....

....validated in [5] where this graph and the auxiliary data structures is applied to the ECO problem. The paper compares the implicit graph and the query data structure with explicit uniform grid approach and Iroute, a well known tile based router for gridless routing used in the Magic layout system [1, 40], as shown in Table 3. The results show that not only this graph representation is very efficient in memory usage 14 Theta smaller than explicit representation and 2 Gamma 3 Theta smaller than Iroute. The queries into the data structure is also very fast. The run time of our maze routing ....

J.K. Ousterhout, G.T. Hamachi, R.N. Mayo, W.S. Scott, and G.S. Taylor. Magic: A VLSI layout system. In Proc. 21st Design Automaton Conference, pages 152--159, Jun 1984.

....in height of the cells in the Reorder Buffer row to the corresponding cells in the Instruction Window row, a direct one to one connection between the valid signal from the VAL BIT cell to the Reorder Buffer is not possible. To avoid tedious hand routing, the auto router available with MAGIC [13] can be used to generate the routing channel between them. 22 3.3 Instruction Window All information pertaining to an instruction is stored in the Instruction Window (including its opcode, source operands, destination tag, ready bit, issued bit, and the PC in case of conditional branch ....

J. K. Ousterhout, G. T. Hamachi, R. N. Mayo, W. S. Scott, and G. S. Taylor. The Magic VLSI Layout System. IEEE Design & Test of Computers, February 1985.

....related to node r as extracted from circuit layouts, V r is the voltage swing on the node, and V dd is the supply potential. We measure energy for the complete register access including bypass muxing and latching. We designed circuits to run at 2.5 V in a 0.25#mCMOS technology from TSMC. Magic [5] was used for layout, and the SPACE 2D extractor [8] was used to extract layout parasitics for circuit simulation, including capacitance to the substrate, fringe capacitance, crossover coupling capacitance, and capacitance between parallel wires. HSpice was used to simulate the extracted netlist ....

J. Ousterhout, G. Hamachi, R. Mayo, W. Scott, and G. Taylor. Magic: A VLSI Layout System. Proc. 21st Design Automation Conference, pages 152--159, 1984.

....enables detection of all design rule violations. Other notable examples include raster plotting, fault extraction [14] pattern generator tape generation, and bipolar device recognition. The reduced memory requirements eliminate the need to employ multiple corner stitched planes as in Magic [1, 15], thereby avoiding plane cross registering overhead. This is especially convenient in case of strong interactions between different masks. Indeed, the fragmentation of the tile structure simplifies e.g. computation of coupling capacitances. For example, the exact overlap region (for parallel plate ....

John K. Ousterhout, Gordon T. Hamachi, Robert N. Mayo, Walter S. Scott, and George S. Taylor, "Magic: A VLSI Layout System," Proc. 21st Design Automation Conference, Albuquerque, New Mexico, pp. 152-159 (Jun. 25-27, 1984).

....as a collection of individual gates. In addition, several circuits may be combined in hierarchical fashion to create a larger circuit. We have currently implemented layout procedures for these three types of circuits. These procedures make used of several tools in the Berkeley MAGIC[7] and OCTTOOLS[8] packages. At the present time there are several steps that must be completed manually, but as the tools evolve, less and less manual intervention will be required. The first step in creating layouts is to break the circuit into a collection of ROMs, PLAs, and standard cell blocks. Each of these ....

J. K. Ousterhout, G. T. Hamachi, R. N. Mayo, W. S. Scott, G. S. Taylor, "The Magic VLSI Layout System," IEEE Design and Test of Computers, Vol. 2, No. 1, Feb. 1985.

....of the hybrid is Theta(nL 3=4 ) as compared to an area of Theta(nL) in two dimensions. To study the empirical complexity of this processor, our research group implemented VLSI layouts of the Ultrascalar I, the Ultrascalar II, and the hybrid register datapaths using the Magic design tools [11]. Our layouts for varying numbers of outstanding instructions confirm the scaling properties of the various processors. Moreover, the layouts demonstrate the practical advantages of the hybrid for foreseeable values of n and L. We have chosen to implement a very simple RISC instruction set ....

J. K. Ousterhout, G. T. Hamachi, R. N. Mayo, W. S. Scott, and G. S. Taylor. Magic: A VLSI layout system. In ACM IEEE 21st Design Automation Conference, pages 152--159, Los Angeles, CA, USA, June 1984. IEEE Computer Society Press. (a) (b)

....capacitance related to node r. The parameters used in this energy estimation model are based on a 0.6 # n well CMOS process technology with 3.3V power supply and two layers of metal. The design of register file and bypassing network is based on the T0 design [1] and is laid out using Magic [12]. The layout to circuit extraction tool, Space [17] is used to extract a circuit netlist for further circuit simulation. Space extracts capacitance to the substrate, fringe capacitance, crossover coupling capacitance, and capacitance between parallel wires. Hspice [11] a circuit simulator, is ....

J. Ousterhout, G. Hamachi, R. Mayo, W. Scott, and G. Taylor. Magic: A VLSI Layout System. Proc. 21st Design Automation Conference, pages 152--159, 1984.

....to search for the routes. Table I shows a summary of the examples used here. The results presented in this section were collected on a 168MHz Sun Ultra 1 workstation with 128MB of memory. We also compare our algorithm with Iroute, a tile based interactive router in Magic layout systems [18] [19]. Table II shows a comparison of memory usage between explicit representation and implicit representation. Please note that the estimation of uniform grid uses the common TABLE II MEMORY USAGE OF DIFFERENT CONNECTION GRAPH (MB) Ex. Uniform Grids Non Uniform Grids Iroute Explicit Implicit ....

J. Ousterchout, G. Hamachi, R. Mayo, W. Scott, and G. Taylor, "Magic: a vlsi layout system," Proc. 21st Design Automaton Conference, no. 1, pp. 152--59, 1984.

....substantially reduced memory bandwidth, resulting in dramatically reduced chip complexity. To study the empirical complexity of this processor, our research group implemented VLSI layouts of the Ultrascalar I, the Ultrascalar II, and the hybrid register datapaths using the Magic design tools [11]. Our layouts for varying numbers of outstanding instructions confirm the processors s scaling properties. Moreover, the layouts demonstrate the practical advantages of the hybrid for foreseeable values of n and L. We have chosen to implement a very simple RISC instruction set architecture. Our ....

J. K. Ousterhout, G. T. Hamachi, R. N. Mayo, W. S. Scott, and G. S. Taylor. Magic: A VLSI layout system. In ACM IEEE 21st Design Automation Conference, pages 152--159, Los Angeles, CA, USA, June 1984. IEEE Computer Society Press.

....notes. 7.1.1. Workloads and Methodology We used a variety of workloads in simulating the various TLB configurations, including several SPECmarks, plus other workloads meant to anticipate more demanding workloads. Tree is a recursive, data intensive benchmark written in C Scheme [11] Magic [62] is a VLSI layout tool. In this run it was extracting the MultiTitan CPU chip [44] We also used a multi tasking workload, running the following programs: gcc . magic extracting the MultiTitan CPU chip . ld loading magic . tree with a 10 megabyte heap . a loop running the shell programs cp, ....

John K. Ousterhout, G. Hamachi, Robert Mayo, W. Scott, and G.S. Taylor. "The Magic VLSI Layout System". IEEE Design and Test of Computers 2, 1 (February 1985), 19-30.

....sake of brevity. The significant difference is that the optimal widths for the elements will be found in one iteration. 2.4 Examples The results of the layout optimization are shown in Figures 3(b) and 4. The uncompacted layout of Figure 3 is a part of the layout generated by the router of MAGIC [31] layout editor from the netlist of example3b of [36] The layout shown in Figure 3(a) is generated by the compactor PLOW [31] with automatic jog insertion, straightening and with minimum horizontal length of 12 . The layout generated by our algorithm is shown in Figure 3(b) To characterize the ....

....Examples The results of the layout optimization are shown in Figures 3(b) and 4. The uncompacted layout of Figure 3 is a part of the layout generated by the router of MAGIC [31] layout editor from the netlist of example3b of [36] The layout shown in Figure 3(a) is generated by the compactor PLOW [31] with automatic jog insertion, straightening and with minimum horizontal length of 12 . The layout generated by our algorithm is shown in Figure 3(b) To characterize the impact of the layout optimization on manufacturing yield, the yield analysis tool Xlaser is used. Probability of failure versus ....

J. K. Ousterhout et al., "Magic: A VLSI Layout System," 21st IEEE Design Automation Conference, 1984, pp. 152-159.

....TIGER project at the U.S. Bureau of Census, the map of the United States will eventually be stored in a database [19] the bit shuffling method is used for a distance preserving mapping. 2) Computer Aided Design (CAD) For example, VLSI design systems need to store many thousands of rectangles [15] representing electronic gates and higher level elements. Rectangles can be divided in pieces; each piece is assigned a z value , according to the Peano curve [13] 3) Computer vision and robotics. 4) Retrieval in large knowledge bases [9] 11] 18] 5) Clustering of data in data base machines ....

Ousterhout, J. K., G. T. Hamachi, R. N. Mayo, W. S. Scott, and G. S. Taylor, "Magic: A VLSI Layout System," 21st Design Automation Conference, pp. 152 - 159, Alburquerque, NM, June 1984.

....savings over the R Gamma tree [3] on real data. 1 Introduction One of the requirements for the database management systems (DBMSs) of the near future is the ability to handle spatial data [28] Spatial data arise in many applications, including: Cartography [29] Computer Aided Design (CAD) [24] [14] computer vision and robotics [2] traditional databases, where a record with k attributes corresponds to a point in a k d space; temporal This research was partially funded by the Institute for Systems Research (ISR) by the National Science Foundation under Grants IRI 9205273 and ....

J. K. Ousterhout, G. T. Hamachi, R. N. Mayo, W. S. Scott, and G. S. Taylor. Magic: a vlsi layout system. In 21st Design Automation Conference, pages 152 -- 159, Alburquerque, NM, June 1984.

....Systems (DBMSs) handle efficiently numbers and character strings, but not multi dimensional data such as boxes, polygons, or even points in a multi dimensional space. Multi dimensional data arise in many applications, including: Cartography [21] Computer Aided Design (CAD) and VLSI design systems [14], 8] computer vision and robotics [1] traditional databases (a record with k attributes corresponds to a point in a k d space) rule indexing in expert database systems [20] etc. Our goal here is to design a method with the following two characteristics: ################## Also with ....

Ousterhout, J. K., G. T. Hamachi, R. N. Mayo, W. S. Scott, and G. S. Taylor, "Magic: A VLSI Layout System," 21st Design Automation Conference, pp. 152 - 159, Alburquerque, NM, June 1984.

....was facilitated by the identical nature of of the exus and the symmetry of the layout. Fig. 6.26 shows how the clocks were routed from the input pads. Drivers were sized to maintain sharp edges. 6.7. 1 Layout and Simulation Layout: Hand crafted cells were laid out using the magic cad tool [90]. The carry select adder cells were obtained from the Lager cell library [64] A micro photograph of the chip is shown in Fig. 6.27. Simulation: Circuit and behavioral simulation were performed using spice [83] and irsim [105] respectively, and the pas assembler was used to generate simulation ....

J. Ousterhout and et al. "The Magic VLSI Layout System". IEEE Design & Test of Computers, pages 19--30, Feb 1985.

....bandwidth linear in the window size, and a a simple serializing memory dependency checker. This version provides O(I) memory bandwidth through the MP modules. To demonstrate the scaling properties of the Ultrascalar, we are currently designing the processor in VLSI using the Magic design tool [10]. We have a complete processor core corresponding to the DP and ES modules in Figure 7. Our processor core executes a simple RISC instruction set architecture without floating point instructions. Figure 8 shows the plot of the second and third metal layers of a 64 station processor core. 9 To ....

J. K. Ousterhout, G. T. Hamachi, R. N. Mayo, W. S. Scott, and G. S. Taylor. Magic: A VLSI layout system. In ACM IEEE 21st Design Automation Conference, pages 152--159, Los Angeles, CA, USA, June 1984. IEEE Computer Society Press.

....data arise in many applications, to name the most important: 1) Cartography. Maps could be stored and searched electronically, answering efficiently geometric queries [3] 19] 2) Computer Aided Design (CAD) For example, VLSI design systems need to store many thousands of rectangles [15] [9] representing electronic gates and higher level elements. 3) Computer vision and robotics. 4) Rule indexing in expert database systems [22] In this proposal rules are stored as geometric entities in some multi dimensional space defined over the database. Then, the problem of searching for ....

J. K. Ousterhout, G. T. Hamachi, R. N. Mayo, W. S. Scott, and G. S. Taylor, "Magic: A VLSI Layout System," 21st Design Automation Conference , pp. 152 - 159 , June 1984.

....and the EDA industry was established in the early 1980s. We have seen the impact of similar changes in user interaction technologies. For example, symbolic layout entry moved from character based CRT approaches[4] to stick diagrams on vector displays[5] to today s raster fill abstractions (e.g. [6,7]) In each case, the layout methodology that could be expressed by the display hardware and associated software ultimately determined the layout data structure and most suitable compaction algorithm. This infrastructure is always evolving and at certain times the changes are so profound that they ....

J. Ousterhout, et al., "Magic: A VLSI Layout System," Proc. 21 st ACM/IEEE Design Automation Conf., pp.152-159, June 1984.

....a function of the geometric characteristics of the R tree. 1 Introduction One of the requirements for the database management systems (DBMSs) of the near future is the ability to handle spatial data. Spatial data arise in many applications, including: Cartography [27] Computer Aided Design (CAD) [22] [12] computer vision and robotics [2] traditional databases, where a record with k attributes corresponds to a point in a k d space; temporal databases, where time can be considered as one more dimension [18] scientific databases, with spatial temporal data, etc. Currently on sabbatical at ....

J. K. Ousterhout, G. T. Hamachi, R. N. Mayo, W. S. Scott, and G. S. Taylor. Magic: a vlsi layout system. In 21st Design Automation Conference, pages 152 -- 159, Alburquerque, NM, June 1984.

....However, when 14 PERFORMANCE IMPLICATIONS OF MULTIPLE POINTER SIZES larger pointers push the working set beyond the size of a cache or real memory, small pointers may show a dramatic advantage. 5.3. Corner stitching in the Magic CAD system Many VLSI designers employ the Magic CAD system [19] to lay out and process their chips. Most VLSI designs can be expressed as a set of rectangles; Magic represents these rectangles and their positions using an algorithm called corner stitching [18] A Tile, the basic object in the corner stitching algorithm, has this structure: x,y) L,X ....

John K. Ousterhout, Gordon T. Hamachi, Robert N. Mayo, Walter S. Scott, and George S. Taylor. The Magic VLSI Layout System. IEEE Design & Test of Computers 2(1):19-30, February, 1985. 3

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J. Ousterhout, G. Hamachi, R. Mayo, W. Scott, and G. Taylor, "Magic: A VLSI layout system," in Proc. 21st Design Automaton Conf., June 1984.

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John K. Ousterhout, Gordon T. Hamachi, et al. Magic: A VLSI layout system. In Proceedings of the 21th ACM/IEEE DAC, pages 152--159, Albequerque, NM, June 1984.

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John K. Ousterhout , Gordon T. Hamachi , Robert N. Mayo , Walter S. Scott , George S. Taylor, "Magic: A VLSI Layout System", Proceedings of the 21 st Design Automation Conference, June 1984 .

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J. K. Ousterhout, G. T. Hamachi, R. N. Mayo, W. S. Scott, G. S. Taylor, "Magic: A VLSI Layout System", Proceedings of the 21 st Design Automation Conference, June 1984.

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J. K. Ousterhout, G. T. Hamachi, et al. Magic: A VLSI layout system. In Proceedings of the 21th ACM/IEEE DAC, pages 152--159, Albequerque, NM, June 1984.

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John K. Ousterhout, G. T. Hamachi, R. N. Mayo, W. S. Scott, and G. S. Taylor. Magic: a VLSI layout system. In Proceedings of the 21st Design Automation Conference, pages 152--159, 1984.

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John K. Ousterhout, Gordon T. Hamachi, Robert N. Mayo, Walter S. Scott, and George S. Taylor. Magic: A VLSI layout system. In Proceedings of the Design Automation Conference, pages 152--159, 1984.

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