Chen C., and Sarrafzadeh M. An effective algorithm for gatelevel power-delay tradeoff using two voltages. in Proc. of ICCD'99 (Austin TX, 1999), 222-227.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....different pipelines with different speeds for energy optimization [2] Zhang et al. 13] propose compiler optimization techniques for exploiting slack in VLIW processor with decreasing the energy consumption as the objective. Chen et al. proposed a slack distribution algorithm for logic circuits [4]. Given a network of logic gates represented with a Directed Acyclic Graph (DAG) this algorithm utilizes the available slack in the network as delay budgets to logic gates. The authors report improvements over the Zero Slack Algorithm [11] however they have the assumption of continuous possible ....

C. Chen, X. Yang and M. Sarrafzadeh. "An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two Voltages". In International Conference on Computer Aided Design, 2000.

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Chen C., and Sarrafzadeh M. An effective algorithm for gatelevel power-delay tradeoff using two voltages. in Proc. of ICCD'99 (Austin TX, 1999), 222-227.

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C. Chen, X. Yang and M. Sarrafzadeh. "An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two Voltages". In International Conference on Computer Aided Design, 2000.

....3.2. If a given directed acyclic graph is a tree, the MISA produces an optimal budget management instance by simply selecting all leaves of subtrees in the slacksensitive graph (i.e. G t (#) as a maximum independent set. Based on the above discussions, we have the following theorem (see [6] and [7] for proof) THEOREM 3.3. The time complexity of the MISA algorithm is O(K ) where n and K are the number of vertices and the number of distinct slacks in a given graph, respectively. The space complexity of the algorithm is O(n ) in the worst case. In the above theorem, the value of K ....

C. Chen and M. Sarrafzadeh, An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two Voltages, in Proceedings of the International Conference on Computer Design, pp. 222--227, 1999.

....it helps us in gaining some understanding of the basic concepts and provides a good foundation for more restricted instances. We use the Maximum Independent Set al..gorithm (MISA) to solve this problem instance. This algorithm was proposed by Chen et al. for slack distribution in logic circuits [3]. Given a network of logic gates represented with a Directed Acyclic Graph (DAG) this algorithm determines the optimal distribution of available slack in the network as delay budgets to logic gates. Algorithm I extends MISA for solving the resource unconstrained problem. Given a DFG and a latency ....

....Outline: The scheduling problem without the resource constraints simply reduces to delay budgeting for a logic network in the form of a DAG. A DFG is basically a DAG. MISA produces optimal slack assignment and attaches these slacks as delay budgets to nodes in a circuit. Detailed proof is given in [3]. Therefore, the same optimal slack distribution is used. While doing the final ASAP scheduling, the increase of operation delay is just for making sure that the final schedule has the same total slack as computed by MISA. It does not represent the real operation delays. Finally, we note that the ....

C. Chen, X. Yang and M. Sarrafzadeh, "An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two Voltages," In Proc. International Conference on Computer Aided Design, Nov 2000.

....of the LCs at the interface of and , we target minimizing the number of LCs by using what we call the constrained Fiduccia Mattheyses [6] algorithm. By specifying different timing constraints, the proposed technique is also able to provide the power delay tradeoff with two supply voltages [22]. The design flow of power optimization with dual voltages is shown in Fig. 2 (other layout structures can be found in [16] II. BACKGROUND A technology mapped network can be represented as a directed acyclic graph . A node corresponds to a gate in the network (The terms gate and node will ....

C. Chen and M. Sarrafzadeh, "An effective algorithm for gate-level power-delay tradeoff using two voltages," in Proc. Int. Conf. Computer Design (ICCD), Austin, TX, Oct. 1999, pp. 222--227.

....v 2 , v 3 , v 4 . Also it is assumed in the figure that the arrival times for the inputs are zero, and the required time for the output (i.e. node v 4 ) is 8. The arrival times and required times for other nodes, as shown, are computed using equation (1) The initial slack distribution is S(V) [5, 5, 5, 5], and the total slack is S(V) 20. If we assign D 1 D(V) 2, 1, 1, 1] to the graph, the slack distribution is updated to be S D1 (V) 1, 2, 1, 1] 0, which means that D 1 D(V) is an effective slack assignment. Similarly, one can verify that DmD(V) 5, 5, 0, 0] is also the effective slack ....

....slack distribution is S(V) 5, 5, 5, 5] and the total slack is S(V) 20. If we assign D 1 D(V) 2, 1, 1, 1] to the graph, the slack distribution is updated to be S D1 (V) 1, 2, 1, 1] 0, which means that D 1 D(V) is an effective slack assignment. Similarly, one can verify that DmD(V) [5, 5, 0, 0] is also the effective slack assignment which leads to the potential slack PS = D mD(V) 10, and S Dm (V) 0. Note that the converse of Lemma 1 is not necessarily true. For instance, another slack assignment D 2 D(V) 2, 2, 2, 1] also leads to zero slack distribution, i.e. S D2 (V) 0. ....

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C. Chen and M. Sarrafzadeh, "An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two Voltages," in Proceedings of ICCD, pp.222-227, 1999.

....leads to potential slack denoted by PS, i.e. PS = D mD(V) D max DD(V) subject to S D (V) 0, then the resultant slack distribution S Dm (V) 0. Fig. 1 shows a four node example where the delay distribution is assumed to be D(V) 1 1 1 1] Initially, the slack distribution is S(V) [5 5 5 5], and the total slack is S(V) 20. D 1 D(V) 2 1 1 1] is an effective slack assignment since S D1 (V) 1 2 1 1] 0. DmD(V) 5 5 0 0] leads to potential slack PS = D mD(V) 10, and S Dm (V) 0. Since s(v i ) is the upper bound of incremental delay for node v i while keeping safety of ....

....S Dm (V) 0. Fig. 1 shows a four node example where the delay distribution is assumed to be D(V) 1 1 1 1] Initially, the slack distribution is S(V) 5 5 5 5] and the total slack is S(V) 20. D 1 D(V) 2 1 1 1] is an effective slack assignment since S D1 (V) 1 2 1 1] 0. DmD(V) [5 5 0 0] leads to potential slack PS = D mD(V) 10, and S Dm (V) 0. Since s(v i ) is the upper bound of incremental delay for node v i while keeping safety of G, any effective slack is no more than total slack of G. In Fig. 1, for example, PS = 10, while total slack S(V) 20. For a given circuit, ....

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C. Chen and M. Sarrafzadeh, "An Effective Algorithm for GateLevel Power-Delay Tradeoff Using Two Voltages," in Proceedings of ICCD, pp.222-227, 1999.

....budget management on G is that different budget management can lead to the same slack distribution. Figure 2 shows fragment of an example graph, where the delay distribution is initially assumed to be D(V) 1 1 1 1] Note that I and O are not shown in the figure) One can verify that D 1 D(V) [5 5 0 0] and D 2 D(V) 2 2 2 1] are two different effective budget management on this graph. However, the resultant slack distributions are same, i.e. SD1 (V) SD2 (V) 0. Furthermore, it can be observed that for an optimal budget management DmD(V) the resultant slack distribution must be zero, ....

.... k ) 5) By finding maximum effective budgets in G k 1 and G k , respectively, we can obtain an optimal budget management for G, which leads to maximum effective budget Bm = DG D(V) DGk 1 D(V) DGk D(V k ) Based on the above discussions, we have the following theorem (see [5] and [6] for proofs) Theorem 3.2. The time complexity of MISA algorithm is O(Kn 3 ) where n and K are the number of vertices and the number of different slacks in a given graph, respectively. 12 For two different timing constraints T a and T b (say, T a T b ) on G, we have S a (V) S b ....

[Article contains additional citation context not shown here]

C. Chen and M. Sarrafzadeh, "An Effective Algorithm for Gate-Level Power-Delay Tradeoff using Two Voltages," in Proceedings of International Conference on Computer Design, pp.222-227, 1999.

....small slack does not imply that the slacks of all its transitive fanins are also small. A linear programming approach was also proposed [18] to address the dual voltage problem. However, it is based on the delay balanced configurations whose generation requires very expensive computation cost. In [6], a Two Voltage Power Optimization (TVPO) algorithm is proposed to reduce power by translating the power optimization problem into the Maximal Weighted Independent Set (MWIS) problem and allowing as many gates as possible working at 7 V low . The number of level converters at the boundary of ....

....library. 12] defines completeness of a gate library for gate sizing. A more complete library would definitely improve the flexibility of the algorithm. The execution time of our algorithm using our fast heuristic for circuit C1908 is 85.87 seconds. The execution time using the MWIS 15 approach [6] is reported as 117.7 seconds for Library A, 136.6 seconds using Library B, 256.6 seconds using Library C and 1485.7 seconds using Library D. We are not reporting a complete comparison with the simultaneous VS and GS technique using a MWIS approach as the gate libraries used by them was different ....

C.Chen and M.Sarrafzadeh, An effective algorithm for gate-level power-delay tradeoff using two voltages, International Conference on Computer Design, pp. 222-227, October 1999

....VS with power red. of 15.4 after SIMUL with power red. of 16.1 Fig. 2. Slack distribution and power reduction for circuit 9symml 2 These are average values over all types of gates. 3 In all experimental results, the power consumption includes the power penalty due to level converters [5]. before optimization TABLE I POWER REDUCTION ( WITH DIFFERENT GATE LIBRARIES (USING V high = 5.0 V AND V low = 3.5 V) Library A Global completeness: 0.08 Local completeness: 0.78 Library B Global completeness: 0.37 Local completeness: 0.85 Library C Global completeness: 0.08 ....

C. Chen and M. Sarrafzadeh, "An effective algorithm for gate-level power-delay tradeoff using two voltages", International Conference on Computer Design, pp.222-227, October 1999.

....slack does not imply that the slacks of all its transitive fanins are also small. A linear 7 programming approach was also proposed [18] to address the dual voltage problem. However, it is based on the delay balanced configurations whose generation requires very expensive computation cost. In [6, 19], a Two Voltage Power Optimization (TVPO) algorithm is proposed to reduce power by translating the power optimization problem into the Maximal Weighted Independent Set (MWIS) problem and allowing as many gates as possible working at V low . The number of level converters at the boundary of ....

....the library. 12] defines completeness of a gate library for gate sizing. A more complete library would definitely improve the flexibility of the algorithm. The execution time of our algorithm using our fast heuristic for circuit C1908 is 85.87 seconds. The execution time using the MWIS approach [6] is reported as 117.7 seconds for Library A, 136.6 seconds using Library B, 256.6 seconds using Library C and 1485.7 seconds using Library D. We are not reporting a complete comparison with the combined VS and GS technique using a MWIS approach as the gate libraries used by them was different than ....

C.Chen and M.Sarrafzadeh, An effective algorithm for gate-level power-delay tradeoff using two voltages, International Conference on Computer Design, pp. 222-227, October 1999

....increased gate delays do not diminish the desired throughput. The slack time of gate v is defined to be s(v) r(v) a(v) 13] where r(v) and a(v) are the required time and arrival time of gate v, respectively. Most of prior work on voltage scaling have focused on behavioral and or logic levels [5, 6, 7, 8, 9]. Due to the very limited accuracy with power and delay modeling at these levels, it is difficult, if not impossible, to predict exactly whether the power reduction in these levels does result in the final power saving. For instance, important parameters (such as wiring capacitance) in power ....

....layout stage, and the final placement had to conform to some specified ordering of high voltage and low voltage cells. In this paper, we will address power optimization issues with dual supply voltages. In the logic level, we use the framework of SIS [12] to implement dual voltage design [9], which gives an estimate of gate power reduction associated with dual voltage technique. In the physical level, we use simulated annealing with additional constraints for placement followed by some post processing with an ultimate goal of reducing power. This paper is organized as follows. In ....

[Article contains additional citation context not shown here]

C. Chen and M. Sarrafzadeh, "An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two Voltages," In International Conference on Computer Design, Oct. 1999, pp.222-227.

....while gates on the non critical paths are allowed to work with a lower voltage (V low ) In [4] Usami reported a Cluster Voltage Scaling (CVS) scheme which uses a Depth First Search from the primary outputs to find gates which can be operated at V low under the given timing constraints. In [6], a Two Voltage Power Optimization (TVPO) algorithm is proposed to reduce power by translating power optimization problem into the Maximal Weighted Independent Set (MWIS) problem and allowing as many gates as possible working at V low . The number of level converters at the boundary of ....

....the library. 12] defines completeness of a gate library for gate sizing. A more complete library would definitely improve the flexibility of the algorithm. The execution time of our algorithm using our fast heuristic for circuit C1908 is 85.87 seconds. The execution time using the MWIS approach [6] is reported as 117.7 seconds for Library A, 136.6 seconds using Library B, 256.6 seconds using Library C and 1485.7 seconds using Library D. We are not reporting a complete comparison with the simultaneous VS and GS technique using a MWIS approach as the gate libraries used by them was different ....

C.Chen and M.Sarrafzadeh, An effective algorithm for gatelevel power-delay tradeoff using two voltages, International Conference on Computer Design, pp. 222-227, October 1999

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