D. Dobberpuhl et al., "A 200-MHz 64-bit dual-issue CMOS microprocessor, " Digital Tech. J., vol. 4, pp. 35--50, 1992.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....A trend in modern high speed, high density CMOS VLSI circuits is decreasing feature sizes as well as increasing chip dimensions. The delay of these highly scaled circuits is now dominated by the interconnect [1] Furthermore, up to 30 of the dynamic power is consumed by the interconnect [2]. In addition to the interconnect delay and power consumption, coupling noise (or crosstalk) between adjacent interconnect lines is also a primary concern for present and future generations of CMOS VLSI circuits [3] 4] 5] Coupling noise between adjacent interconnect can cause disastrous ....

D.W. Dobberpuhl, et al., "A 200-Mhz 64-bit Dual-Issue CMOS Microprocessor," IEEE Journal of Solid-State Circuits, Vol. SC-27, No. 11, pp. 1555-1565, November 1992.

....a match exists assuming an initial correspondence between some part of the subcircuit and given nets and or devices in the netlist. The first approach is to perform a brute force depth first backtracking search from the Table 4 2. Fanout Statistics for Four Netlists Design MR MIPSX[10] NV5[9] EV4[8] Description Router Microprocessor Microprocessor Microprocessor Total Number of Devices 7143 43540 740716 1695691 Total Number of Nets 2867 18572 31224 662214 Average Number of Adjacent Devices per Net 7.47 7.02 7.11 7.68 Excluded Nets Vdd, GND, reset b Vdd, GND, VDD, VSS, Phi1 , Phi2 , Phi3 , ....

D. Dobberpuhl, "A 200-Mhz, 64-bit, Dual-Issue CMOS Microprocessor", IEEE Journal of Solid State Circuits, Vol. 17, No. 11, 1555-1567, November 1992. 90

....synchronous CMOS integrated circuits. I. INTRODUCTION The trend in next generation integrated circuit (IC) technology is towards higher speeds and densities. The total capacitive load associated with the internal circuitry is therefore increasing in both current and next generation VLSI circuits [1], 2] 3] As the operating frequency increases, the average on chip current required to charge (and discharge) these capacitances also increases, while the time during which the current is switched decreases [4] Therefore, a large change of the on chip current occurs within a short period of ....

D. W. Dobberpuhl et al., "A 200-MHz 64-bit Dual-Issue CMOS Microprocessor," IEEE Journal of Solid-State Circuits, Vol. SC--27, No. 11, pp. 1555--1565, November 1992.

.... on chip currents will increase from amperes in 1999 to amperes by [1] Power distribution networks in high complexity CMOS integrated circuits must be able to provide sufficient current to support average and peak power demand within all parts of an integrated circuit [2 4]. The large chip dimensions and on chip average currents require special design strategies to maintain a constant voltage supply within a power distribution network [5, 6] The voltage supply is expected to decrease from volts in to volts by [1] reducing the ....

D. W. Dobberpuhl et al., "A 200-MHz 64-bit Dual-Issue CMOS Microprocessor," IEEE Journal of Solid-State Circuits, Vol. SC-- 27, No. 11, pp. 1555--1565, November 1992.

....average interconnect length has not scaled down with feature size. Therefore, on chip interconnect has become increasingly important [1] The delay of these highly scaled circuits is now dominated by the interconnect [2] 3] Furthermore, up to 30 of the dynamic power is due to the interconnect [4]. Interconnect in CMOS circuits has historically been modeled as a capacitive load [5] Analytic expressions characterizing the propagation delay and short circuit power based on a capacitive model have been previously addressed in the literature [6 9] However, the parasitic interconnect ....

D. W. Dobberpuhl et al., "A 200-MHz 64-bit Dual-Issue CMOS Microprocessor," IEEE Journal of Solid-State Circuits, Vol. SC--27, No. 11, pp. 1555--1565, November 1992.

....designs now require #V to be contained within 10 of Vdd. To achieve this goal, decoupling capacitors are added to minimize the switching noise. For high performance circuits with a cycle time of 5 ns or less, it is estimated that as much as 10 of the chip area may be needed to serve this purpose [6]. Therefore, it is important to estimate and allocate the area needed for on chip decoupling capacitors during the early floor planning stage. The floor planning of flexible decoupling capacitors is restricted by the topological and ordering constraints of the preplaced functional blocks. Given ....

D. Dobberpuhl et al., "A 200-MHz 64-bit dual-issue CMOS microprocessor," IEEE Journal of Solid-State Circuits, pp. 1555--1567, November 1992.

....of four generations of Alpha microprocessors. Some of the data reflects projections made in the referenced papers and therefore may differ from actual characteristics at product shipment. Product Characteristics Year Trans (M) Voltage (V) Clock (MHz) Power (W) Pwr Clk (W MHz) 21064 [1, 2] 1992 1.68 3.3 200 30 0.15 21164 [3, 4] 1995 9.3 3.3 300 50 0.17 21264 [5, 6] 1998 15.2 2.2 575 60 0.10 21364 [7] 2000 01 100 1.5 1000 100 0.10 Because of the inability of circuit level techniques to singlehandedly keep power dissipation to reasonable levels, there has been increasing interest ....

D. Dobberpuhl et al., "A 200MHz, 64-bit, dual-issue CMOS microprocessor," Digital Technical Journal, vol. 4, pp. 35--50, Special Issue 1992.

....tradeoffs for these parameters and have a region of the design space narrowed down, we can then address parameters which have less impact on performance. In this paper, we address the size of the TLB. The physical aspects of our study are based on the dimensions of the Alpha 21064 microprocessor[5, 13]. We scale the processor core and cache dimensions of the 21064 to 0.25 micron technology, and assume the use of a one inch square die. We then use this data to obtain candidate multiprocessor configurations which vary in cache size and number of processors. 1 An experimental version of such a ....

D.P. Dobberpuhl, et al, "A 200MHz, 64-Bit, Dual-Issue CMOS Microprocessor," Digital Technical Journal, Vol. 4, No. 4, pp. 35-50, 1992.

....small; off chip delays affect execution speed only on occasions when the processor is stalled by an on chip cache miss. Examples of the fully integrated approach include most of today s fastest microprocessors, including Intel s i486 [11] and Digital s recently announced 21064 RISC microprocessor [5]. This trend toward increased integration has sounded the death knell for multichip processor implementations. Shortly even mainframe computers the last bastion of the older, multichip design style will be built using fully integrated microprocessors [7] Today mainframes are almost ....

....quantities, and would be less than half that in volume production. While our work was directed toward meeting the demands of ECL designs, some of these packaging techniques may eventually prove useful even for CMOS. Today s fastest and most power hungry CMOS microprocessors dissipate only 30 W, [5] but history suggests that higher dissipations are inevitable. lead photo 6.3 x 4.4 Figure 1: Package for 150W bipolar ECL microprocessor die. PACKAGING A 150 W BIPOLAR ECL MICROPROCESSOR bottom view 6.3 x 4.4 Figure 2: Bottom view of package assembly. PACKAGING A 150 W BIPOLAR ECL ....

D. Dobberpuhl et al. (1992). A 200MHz 64 Bit Dual Issue CMOS Microprocessor. In Proceedings of the 1992 International Solid-State Circuits Conference. San Francisco, California, February, 1992.

....over the entire chip. As feature sizes decrease and chip dimensions increase the relative importance of the clock tree in the overall power consumption increases. For highly pipelined microprocessors like the DEC Alpha the clock power dissipation can be up to 50 of the entire power budget [4]. Similar clock power consumptions can be expected for fine grain systolic arrays or synchronous wafer scale integration circuits. Paper presented at TAU 95. This work was supported in part by NSF grants MIP 9208267 and CDA 9320325. The authors are with the Department of Electrical and Computer ....

D. Dobberpuhl et al. "A 200-MHz 64-bit Dual-Issue CMOS Microprocessor ", IEEE Journal of Solid-State Circuits, pp. 15551567, Nov. 1992.

....which is practically nil for static CMOS. The problem is that because of shrinking device sizes (sub micron) increasing die size and increasing clock frequencies (hundreds of MHz) the dynamic power dissipation increases very much and as a result many new CMOS ICs are extremely power hungry [3]. The dynamic power dissipation for a CMOS gate is [2] P dynamic = C Delta V dd 2 Delta f Delta p t where C is the load capacitance, V dd the power supply voltage, f the clock frequency and p t is the activity factor or the average number of transitions per clock cycle. Usually p t is 1 ....

....circuit. It is then convenient to consider two different average load capacitances [8] ffl one for the internal circuit, C av int , ffl another one for the I O, C av I=O . With this, formula (2) becomes: P dynamic total = P dynamic int P dynamic I=O where P dynamic I=O can be as low as 10 [3] and as high as 80 [4] of the total dynamic power dissipation. Typically for current ICs, P dynamic I=O is half of the total power budget [10, 11] Because C av I=O AE C av int it follows then that n t int AE n t I=O . This is also confirmed by Rent s rule which states that if the complexity of ....

D. Dobberpuhl et al. "A 200-MHz 64-bit DualIssue CMOS Microprocessor", IEEE Journal of Solid-State Circuits, pp. 1555-1567, Nov. 1992.

....however, in terms of power dissipation. Latch models are either very specific and low level Spice like, or relatively incomplete in terms of accounting for all the kinds of events that can occur in a real system. As an example of the interrelationship of latches, performance, and power, Dobberpuhl [4, 5, 6] has reported that 65 of the total power of the 21064 microprocessor was associated with the clock. Given that most of the capacitance driven by clock is in fact the latches, it is clear that they deserve detailed study in their own right. This paper represents an attempt to introduce a new ....

D. Dobberpuhl et al., "A 200-MHz 64-bit dual-issue CMOS microprocessor." IEEE Journal of Solid State Circuits, Vol.27, No.11, November 1992.

....however, in terms of power dissipation. Latch models are either very specific and low level Spice like, or relatively incomplete in terms of accounting for all the kinds of events that can occur in a real system. As an example of the interrelationship of latches, performance, and power, Dobberpuhl [4, 5, 6] has reported that 65 of the total power of the 21064 microprocessor was associated with the clock. Given that most of the capacitance driven by clock is in fact the latches, it is clear that they deserve detailed study in their own right. This paper represents an attempt to introduce a new ....

....4 X = 0 5 S4 Z = 0 Z = 1 X = 1 Z 0 6 S8 C = 0 D = 0 X 1 Z 0 7 S7 8 Q = 0 Y = 0 Y = 1 S3 9 S6 10 Q = 1 Y = 0 Y = 1 Figure 19. State tree of the Alpha 21064 active high latch. 4.1. True single phase latch used in the Alpha 21064 The operation of this latch Fig. 18 is explained in [22] [5] and [21] The main advantages of using the true single phase latches are as follows [5] 1) immunity to race through (in the Alpha 21064 zero delay was allowed between latches, completely freeing the designer from race through considerations) 2) immunity to noise; 3) flexibility, since simple ....

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D. Dobberpuhl et al., "A 200-MHz 64-bit dual-issue CMOS microprocessor." Digital Technical Journal, Vol.4, No.4, 35--50, Special Issue 1992.

....components. The first component is internal circuit capacitance times the average internal circuit transitions, while the second component is external bus capacitance times the average external bus transitions. The distribution of power among these two components is anywhere between 10 bus I O [11] to 80 bus I O [12] depending on the nature of application, implementation technology, etc. On the average, the I O and system busses in a typical IC consume half of the total chip power [7, 13] Much has been done in reducing the internal circuit power, but buses, often considered highly rigid ....

D. Dobberpuhl et al. "A 200-MHz 64-bit Dual-Issue CMOS Microprocessor," IEEE Journal of Solid-State Circuits, pp. 1555-1567, Nov. 1992.

....problems of service and resource complexity as well as the relative expense of client kernel and client server communications. The central resource in Angel is the single address space. Although originally proposed in systems such as MULTICS [6] the introduction of 64 bit processors architectures [7] has renewed interest in this type of operating system structure, with the development of a number of similar systems (including Mungi [8] and Opal [9] In Angel, the single address space is used to unify various, previously independent, resources and as a mechanism to simplify the kernel s ....

Dobberpuhl et al., "A 200Mhz 64-bit Dual Issue CMOS Microprocessor," in International SolidState Circuits Conference, February 1992.

....cycles (average 1 transition per clock cycle) starvation coding and in [20] is called limited weight coding . II. Coding for low power I O The floorplan of a VLSI IC is being formed of the internal circuit surrounded by the I O padframe. The power dissipated at the I O can be as low as 10 [7] and as high as 80 [15] of the total power dissipation. For circuits optimized for low power the power dissipated at the I O is typically around 50 of the total [24] This large I O power dissipation is a consequence of the huge (compared with the internal circuit) dimensions of the devices in ....

D. Dobberpuhl et al. "A 200-MHz 64-bit Dual-Issue CMOS Microprocessor ", IEEE Journal of Solid-State Circuits, pp. 15551567, Nov. 1992.

....arrays and trees have been proposed. The goal is to reduce the number of adders in the critical path in an array like architecture while maintaining sparse wiring and regular layout. The most common solution is to split the full array into odd and even partial products and interleave the additions [3]. This reduces the critical path by almost half as compared to a full array. The wiring is similar to the wiring of full arrays. This paper is an extension of this work, focusing on different architectures that break up the full array into smaller parts and use a combining network (another array ....

D. Dobberpuhl, "A 200MHz 64bit Dual-Issue CMOS Microprocessor.," 1992 IEEE ISSCC digest of technical papers, pp. 106-107.

....We therefore adopted uniform addressing for in core code and data in our earlier Psyche system [52, 53] arguing that the advent of 64 bit architectures would soon eliminate the scarcity of virtual addresses. With the recent release of microprocessors such as the MIPS R4000 and the DEC Alpha [17], we believe that uniform addressing can be adopted without hesitation for large, multi user systems. Moreover, the truly enormous amount of space addressable in 64 bits makes it possible to extend uniform addressing into the file system, and to unify the entire memory hierarchy into an ....

Dobberpuhl and others, "A 200mhz 64 Bit Dual Issue CMOS Microprocessor," Proceedings of the International Solid-State Circuits Conference, February 1992.

....exploiting the resources available in a parallel machine. During the design of Meshix there have been several major advances in the field of computer architecture. This has enabled a new approach to be taken in microkernel design. First, the advent of 64 bit address space processors (e.g. DEC Alpha [7], MIPS R4000 [8] and the custom chip in the KSR 1 [9] Second, the communication devices available to connect computers have dramatically increased in speed (approaching one gigabit sec) 10] The goal of our research is to find the best way to overcome the limitations identified with Meshix (and ....

Dobberpuhl and others, "A 200Mhz 64-bit Dual Issue CMOS Microprocessor," in International Solid-State Circuits Conference, February 1992.

....components. The first component is internal circuit capacitance times the average internal circuit transitions, while the second component is external bus capacitance times the average external bus transitions. The distribution of power among these two components is anywhere between 10 bus I O [11] to 80 bus I O [12] depending on the nature of application, implementation technology, etc. On the average, the I O and system busses in a typical IC consume half of the total chip power [7, 13] Much has been done in reducing the internal circuit power, but buses, often considered highly rigid ....

D. Dobberpuhl et al. "A 200-MHz 64-bit Dual-Issue CMOS Microprocessor," IEEE Journal of Solid-State Circuits, pp. 1555-1567, Nov. 1992.

....complexity and the relative expense of kernel server client communications. 2.1 Simplified resources The central resource in the Angel operating system is a single address space. Although originally proposed in systems such as MULTICS [8] the introduction of 64 bit processor architectures [9, 10] has renewed interest in this type of operating systems structure, other contemporary SASOSs being Mungi [11] and Opal [12] In Angel, this single address space is used to unify various, previously independent resources: Transitory and persistent data is traditionally held in separate entities, ....

Dobberpuhl et al., "A 200Mhz 64-bit Dual Issue CMOS Microprocessor," in International Solid-State Circuits Conference, February 1992.

....simplifies data sharing, helps cache performance, and blurs the distinction between shared memory and distributed memory machines. The SASA is maintained between multiple processors using shared memory techniques. The SASA has become feasible with the appearance of large address space processors [17], enabling many processes to consume addresses from the same range without exhausting the supply. This address space is managed as persistent objects (contiguous groups of pages) Not only does this remove the need for an explicit file system interface (with a different namespace and explicit ....

Dobberpuhl et al., "A 200Mhz 64-bit Dual Issue CMOS Microprocessor," in International SolidState Circuits Conference, February 1992.

No context found.

D. Dobberpuhl et al., "A 200-MHz 64-bit dual-issue CMOS microprocessor, " Digital Tech. J., vol. 4, pp. 35--50, 1992.

No context found.

D. Dobberpuhl, et al., "A 200-MHz 64-bit Dual-issue CMOS Microprocessor," Digital Technology Journal, vol. 4, no. 4, pp. 35-50, 1992.

No context found.

Dan Dobberpuhl, R. Witek, et al. "A 200 MHz 64 bit Dual Issue CMOS Microprocessor." International Solid-State Circuits Conference 1992, February 1992.

No context found.

D. Dobberpuhl et al., "A 200-MHz 64-bit Dual-issue CMOS Microprocessor," Digital Technical Journal, vol. 4, no. 4 (Special Issue 1992): 35--50.

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