#S. Gerstendrfer, H.-J. Wunderlich, "Minimized Power Consumption for Scan-Based BIST", Proc. Int. Test Conference (ITC), pp. 77-84, 1999.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....on the problem of controlling heat dissipation by reducing the average power dissipation [Chou 94] Wang 94, 97ab, 99] Dabholkar 98] Girard 99a] Sankaralingam 00, 01] Chandra 01] Some designfor test (DFT) techniques reduce peak power in addition to average power. In [Hertwig 98] and [Gerstendrfer 99] logic is added to hold the output of the scan cells at a constant value during scan shifting thereby reducing power dissipation. This approach greatly reduces average power, and will avoid peak power problems during scan shifting, but will not help with peak power problems during the capture ....

Gerstendrfer, S., and H.-J. Wunderlich, "Minimized Power Consumption for Scan-Based BIST," Proc. of International Test Conference, pp. 77-84, 1999.

....by a clock running at half the speed of the normal clock. Another TPG based on cellular automata is presented in [19] Modified scan latch and vector inhibition: Scan power can also be reduced by modifying the scan cell and adding gating logic to mask the scan path activity during shifting [20]. This approach coupled with random pattern suppression provides significant power savings during BIST [21] The vector inhibiting technique presented in [21] provides 0278 0070 03 17.00 2003 IEEE a hardware solution to the power minimization problem and is shown to significantly decrease power ....

S. Gerstendrfer and H.-J. Wunderlich, "Minimized power consumption for scan-based BIST," in Proc. Int. Test Conf., 1999, pp. 77--84.

.... Recently TAM scheduling, a special case of test scheduling, has gained interest [7,9] An important issue then is the wrapper used to connect the cores to the TAM [11,15,16,17] Techniques have also been proposed to reduce test power dissipation allowing testing at higher clock frequencies [6,19,21]. In this paper, we combine preemption based test scheduling [8] and scan chain partitioning [1] to a preemptive TAM scheduling technique under power constraint, which we modelled as a Bin packing problem. We also outline a flexible power conscious test wrapper, which is useful to (1) control the ....

....can be reduced by partitioning the scan flip flops into several chains of shorter length. Aerts and Marinssen [1] investigated scan chain partitioning where the constraints are defined by available pins (bandwidth) The shift process also contributes to a major part of the test power consumption [6]. Gerstendrfer and Wunderlich [6] proposed a technique to isolate the scan flip flops during the shift process. However, the approach may cause an effect on the critical path. Test access is eased by placing the core in a wrapper such as Boundary scan [2] TestShell [15] or IEEE P1500 [16] ....

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S. Gerstendrfer and H-J Wunderlich, "Minimized Power Consumption for Scan-Based BIST", Proceedings of IEEE International Test Conference (ITC), pp. 77-84, Atlantic City, NJ, Sep. 1999.

....consumption during scan testing. In particular, we show that we can decrease both peak and average power by using Golomb codes for compressing the scan vectors of IP cores. In this way, there is no need to either reduce the scan clock rate for low power or add blocking logic to the scan cells [5]. The use of a low cost on chip decoder allows us to achieve significant test data compression, and the decompressed scan vectors cause very little switching activity in the scan chains during test application. While we only target scan in power in our compression scheme, we show experimentally ....

S. Gerstendrfer and H.-J. Wunderlich, "Minimized power consumption for scan-based BIST," in Proc. Int. Test Conf., 1999, pp. 77--84.

.... reduce power during test usually at cost of sub optimal FC, in some cases much lower than the one attainable by standard BIST techniques, such as in [7] The above mentioned approaches can be easily adapted for testing of sequential circuits either through customized full scan architectures [8] or non scan ones (e.g. BILBO) Cellular Automata are an attractive solution to test pattern generation due to their good statistical properties [12] In particular, linear CA have been proven isomorphic to LFSR circuits, and incur in lower routing overhead for large bit widths. In this paper ....

S Gerstendrfer, H.-J. Wunderlich, "Minimized Power Consumption for Scan-based BIST", IEEE International Test Conference, 1999, pp. 77-84

....power issues for test are becoming increasingly important [Crouch 99] Techniques for minimizing power during test are needed. Test scheduling algorithms that satisfy power constraints were presented in [Chou 94] Low power BIST techniques were presented in [Wang 97a] Hertwig 98] Wang 99] Gerstendrfer 99] Girard 99, 00] Techniques for minimizing power dissipation when testing combinational circuits were presented in [Wang 94] Dabholkar 98] and for scan circuits in [Wang 97b] Dabholkar 98] Sankaralingam 00] Whetsel 00] The focus of this paper is on the problem of minimizing power ....

Gerstendrfer, S., and H.-J. Wunderlich, "Minimized Power Consumption for Scan-Based BIST," Proc. of International Test Conference, pp. 77-84, 1999.

....test time. With increasing clock frequencies, the time to apply even a million LBIST test patterns will become very low. However, it will cause a lot of power dissipation, as each test pattern requires a large number of shift operations and pseudorandom patterns cause excessive circuit switching [Gerstendrfer 99] Wang 99] In this paper, we propose a new and elegant technique of merging LBIST and external test patterns. The idea is to concurrently fill one subset of the scan chains with pseudo random test data from the PRPG and the remaining scan chains with deterministic test data from an external ....

Gerstendrfer, S., and H-J Wunderlich, "Minimized Power Consumption for Scan-Based BIST," Proc. of International Test Conference, pp. 77-84, Sept. 1999.

....supply ground distribution system are needed. Researchers have begun looking at ways to control power dissipation during test. Test scheduling algorithms that satisfy power constraints were presented in [Chou 94] Low power BIST techniques were presented in [Wang 97a] Hertwih 98] Wang 99] Gerstendrfer 99] Girard 99] Techniques for minimizing power dissipation when testing combinational circuits were presented in [Wang 94] Dabholkar 98] Techniques for minimizing power dissipation during scan testing were presented in [Wang 97b] Dabholkar 98] This paper focuses on the problem of ....

Gerstendrfer, S., and H.-J. Wunderlich, "Minimized Power Consumption for Scan-Based BIST," Proc. of International Test Conference, pp. 77-84, 1999.

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#S. Gerstendrfer, H.-J. Wunderlich, "Minimized Power Consumption for Scan-Based BIST", Proc. Int. Test Conference (ITC), pp. 77-84, 1999.

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S. Gerstendrfer and H-J Wunderlich, "Minimized Power Consumption for Scan-Based BIST", Proceedings of IEEE International Test Conference (ITC), pp. 77-84, Sep. 1999.

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S. Gerstendrfer, H.-J. Wunderlich, "Minimized Power Consumption for Scan-Based BIST", Proc. International Test Conference, pp. 77-84, 1999.

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