J. C. Hoe and Arvind. Hardware Synthesis from Term Rewriting Systems. Technical Report 421 A, Laboratory for Computer Science - MIT, 1999. Home/Search Document Details and Download
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Architectural Specification, Exploration and.. - Ayala-Rincon.. (2002) (Correct)
....languages and proof assistants. In recent years some work on applying rewriting techniques to model and veri cation of digital processors has been developed. In particular, Arvind s group has treated the design of processors over simple architectures [13, 14, 1] and synthesis of digital circuits [8]. Their approach to architectural description was to describe a simple RISC processor using TRS and to translate it to a standard hardware description language for simulation purposes. However, this approach introduces the cost of program translation and detailed hardware simulation, since TRSs ....
J. C. Hoe and Arvind. Hardware Synthesis from Term Rewriting Systems. Technical Report 421 A, Laboratory for Computer Science - MIT, 1999.
Efficient Computation of Algebraic Operations over .. - Ayala-Rincon.. (2003) (Correct)
.... Kapur who has used his well known Rewriting Rule Laboratory RRL for verifying arithmetic circuits [15,14,16] as well as Arvind s group that treated the specification of processors over simple architectures [2,24,25] the rewrite based description and synthesis of simple logical digital circuits [27] and the description of cache protocols over memory systems [26] Also we have contributed in this field by showing how rewriting theory can be applied for the specification of processors over simple architectures (as Arvind s group does) as well as for the purely rewrite based simulation, ....
J.C. Hoe and Arvind, Hardware Synthesis from Term Rewriting Systems, Laboratory for Computer Science - MIT, 421 A, 1999.
A Higher-Level Language for Hardware Synthesis - Sharp, Mycroft (2001) (3 citations) (Correct)
....channel passing facility, all four of HardwareC s structuring primitives (block, process, procedure and function) can be seen as special cases of SAFL fun declarations (see Section 2.3) Since SAFL only requires a single structuring primitive it yields a simpler semantics. Hoe and Arvind [5] describe TRAC: a hardware synthesis system which generates synchronous hardware from a high level speci cation expressed as a termrewriting system. Broadly speaking, terms correspond to states and rules correspond to combinatorial logic which calculates the next state of the system. Restrictions ....
Hoe, J., and Arvind. Hardware synthesis from term rewriting systems. In Proceedings of X IFIP International Conference on VLSI (1999).
High-level Synthesis of Pipelined Circuits from Modular.. - MARINESCU, RINARD (2001) (Correct)
....each pipeline stage at each clock cycle; there is no notion of synchronicity. Several speci cation and veri cation systems have taken an approach similar to ours, based on describing the behavior of a system by a state transition system [7] 14] Closely related to our research, Hoe and Arvind [15] develop a method for hardware description and synthesis based on an operation centric approach. 8. Conclusions This paper presents a new approach for hardware synthesis. The designer uses a design language based on connecting modules with asynchronous queues. The synthesis algorithm eliminates ....
J. Hoe and Arvind. Hardware synthesis from term rewriting systems. In VLSI: Systems on a chip, Lisbon, Portugal, December 1999.
Higher-Level Hardware Synthesis - Sharp (2002) (Correct)
....a behavioural specification into a structural implementation by means of a library of correctness preserving transformations. DDD has been tested on a number of large case studies, including the derivation of a complete microprocessor [28] 2. 4 Term Rewriting Systems Hoe and Arvind describe TRAC [69]: a hardware synthesis system which generates synchronous hardware from a high level specification expressed in a term rewriting system [15] Broadly speaking, terms correspond to states and rules correspond to combinatorial logic which calculates the next state of the system. Restrictions imposed ....
HOE, J., AND ARVIND. Hardware synthesis from term rewriting systems. In Proceedings of X IFIP International Conference on VLSI (1999).
Proving the Correctness of a Complete Microprocessor - Jacobi, Kroening (2000) (Correct)
....Machines to Verilog HDL The implementation above is specified as mathematical machine in the PVS language. All proofs rely on this specification. This specification is converted into a synthesizable subset of Verilog HDL [22] This is done automatically by a program. A similar approach is made in [23]. The program is limited to convert mathematical machines, i.e. it takes a configuration set, an initial configuration, and a transition function as inputs. This tool is not limited to in order designs. 5 Future Work We are in progress of extending the design with a mechanism for speculative ....
James C. Hoe and Arvind. Hardware synthesis from term rewriting systems. In Proc. of VLSI'99, Lisbon, Portugal, 1999.
Using Term Rewriting Systems to Design and Verify Processors - Arvind, Shen (1998) (17 citations) (Correct)
....(e.g. PVS) and model checkers (e.g. Murphi) can alleviate this problem; we are exploring the use of such tools in our verification effort. Finally, we are also developing a compiler for hardware synthesis from TRS s. It translates TRS s into a standard hardware description language like Verilog [5]. We restrict the generated Verilog to be structural, so that commercial tools can be used to go all the way down to gates and layout. The grammar of the terms, when augmented with details like instruction formats and sizes of various register files, buffers, memories etc, precisely specifies the ....
....GCD Circuit Hardware Synthesis of GCD James C. Hoe, MIT Euclides algorithm for computing the greatest common divisor of two numbers can be expressed as follows in TRS notation: GCD(x,y) if x y GCD(y,x) GCD(x,y) if x y and y 6= 0 GCD(x y,y) TRAC, Term Rewriting Architectural Compiler [5], generates a Verilog description for the circuit shown in Figure 11. The ffi wires represent the new state values while the wires represent the firing condition of the corresponding rules. After synthesis by the latest Xilinx s tools, the circuit with 32 bit x and y registers runs at 40.1 MHz ....
James C. Hoe and Arvind. Hardware Synthesis from Term Rewriting Systems. CSG Memo 421, Laboratory for Computer Science, MIT, 1999.
Proving the Correctness of Pipelined Micro-Architectures - Kroening, Paul, Mueller (2000) (1 citation) (Correct)
....as mathematical machine in the PVS language. All proofs rely on these specifications. In order to get real hardware, e.g. which can be put on an ASIC or FPGA, this specification is converted into a subset of Verilog [19] This is done automatically by a program. A similar approach is made by [9]. The program is limited to convert mathematical machines, i.e. it takes a configuration set, an initial configuration, and a transition function. This tool is not limited to in order designs. 7 Future Work This paper does only covers data consistency and does not provide a proof that the ....
James C. Hoe and Arvind. Hardware synthesis from term rewriting systems. In In Proc. of VLSI'99, Lisbon, Portugal, 1999.
Synthesis of Operation-Centric Hardware Descriptions - James Hoe Dept (2000) (5 citations) Self-citation (Hoe) (Correct)
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J. C. Hoe and Arvind. Hardware synthesis from term rewriting systems. In Proceedings of X IFIP International Conference on VLSI (VLSI 99), Lisbon, Portugal, November 1999.
Synthesis of Operation-Centric Hardware Descriptions - Hoe, Arvind (2000) (5 citations) Self-citation (Hoe) (Correct)
.... have been implemented in the Term Rewriting Architectural Compiler (TRAC) TRAC accepts TRSPEC descriptions and outputs synthesizable structural descriptions in the Verilog Hardware Description Language [18] The TRSPEC language is an adaptation of TRS for operation centric hardware description [11]. This section discusses the synthesis of a fivestage pipelined implementation of the MIPS R2000 ISA (as described in [12] The TRSPEC description implements all of the MIPS R2000 integer ISA except: multiple divide; partial word or non aligned load stores; coprocessor interfaces; privileged and ....
J. C. Hoe and Arvind. Hardware synthesis from term rewriting systems. In Proceedings of X IFIP International Conference on VLSI (VLSI 99), Lisbon, Portugal, November 1999.
Electronic Notes in Theoretical Computer Science 70 No. 6 (2002) - Url Http Www (Correct)
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J. C. Hoe and Arvind. Hardware Synthesis from Term Rewriting Systems. Technical Report 421 A, Laboratory for Computer Science - MIT, 1999.
Architectural Speci - Cation Exploration And (2002) (Correct)
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J. C. Hoe and Arvind. Hardware Synthesis from Term Rewriting Systems. Technical Report 421 A, Laboratory for Computer Science - MIT, 1999.
Architectural Specification and Simulation Through.. - Mauricio.. (Correct)
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J. C. Hoe and Arvind. Hardware Synthesis from Term Rewriting Systems. Technical Report 421 A, Laboratory for Computer Science - MIT, 1999.
ACRES Architecture and Compilation - Ang, Schlansker (2004) (Correct)
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J.C. Hoe and Arvind. Hardware Synthesis from Term Rewriting Systems. In Proceedings of the X IFIP International Conference on VLSI, Lisbon, Portugal, 1999. 79
Higher-Level Techniques for Hardware Description and Synthesis - Mycroft, Sharp (Correct)
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Hoe, J., and Arvind. Hardware Synthesis from Term Rewriting Systems. In Proceedings of X IFIP International Conference on VLSI (1999).
High Level Synthesis from Sim-nML Processor - Basu (1999) (Correct)
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Hoe, J. C., and Arvind. "Hardware Synthesis from Term Rewriting Systems". Proc. of VLSI'99" (December 1999). ftp://csg-ftp.lcs.mit.edu/pub/papers/csgmemo/memo421a. ps.gz .
Designing Arithmetic Digital Circuits via Rewriting-Logic - Ayala-Rincon.. (Correct)
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J. C. Hoe and Arvind. Hardware Synthesis from Term Rewriting Systems. In Proc. of the 10th IFIP International Conference on VLSI - VLSI'99, pages 595--619. Kluwer, 1999.
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