Lienig J. (1997) A Parallel Genetic Algorithm for Performance Driven VLSI Routing. IEEE Transactions on Evolutionary Computation Vol. I. No.1 :29-39 Home/Search Document Details and Download
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Evolutionary And Adaptive Synthesis Methods (ch.8 of Formal .. - Lee, Ma, Antonsson (Correct)
....and keep only those with good fitness values for the next iteration. These methods have been demonstrated to successfully synthesize novel design configurations of: VLSI layouts (Wong et al. 1989; Chatterje and Hartley, 1990; Cheng and Gen, 1996; Naito et al. 1996; Salami et al. 1996; Lienig, 1997a; Lienig, 1997b; Mihaila, 1997; Drechsler, 1998) structures (Goldberg, 1987; Bense and Kikuchi, 1988; Chapman et al. 1994; Reddy and Cagan, 1995a; Reddy and Cagan, 1995b; Chapman and Jakiela, 1996; Duda and Jakiela, 1997; Shea et al. 1997; Shea and Cagan, 1997; Campbell, 2000; Jakiela et al. ....
....to optimize layouts (or placement of components) of different systems. For example, the VLSI electronic chip layout design problem (Wong et al. 1989; Chatterje and Hartley, 1990; Cheng and Gen, 1996; Drechsler, 1998) and automated synthesis of topology and sizing of analog electrical circuits (Lienig, 1997a; Lienig, 1997b; Mazumder and Rudnick, 1999) Field programmable gate arrays (FPGA) or reconfigurable hardware, has been the subject of much research, with (Mihaila, 1997; Naito et al. 1996; Salami et al. 1996) being a small sample of such work. Another example is the pipe network layout design ....
Lienig, J. (1997a). A parallel genetic algorithm for performance-driven VLSI routing. IEEE Transactions on Evolutionary Computation, 1(1):29--39.
Algorithmic and Theoretical Problems Related to the Physical.. - Karro (2000) (Correct)
....each net, subject to the restrictions imposed by the switch blocks. Specification Logic Design Circuit Design Physical Design Fabrication Testing Partitioning Placement Routing Compaction Chip x = a b c a c b Figure 4. 1: The stages of chip design and electronic design automation [64]. Traditionally each of these steps are performed sequentially: the output of one phase 4.2. The Phases of Design Automation 30 becomes the input of the next. We do not believe that this is the best approach, and discuss an alternative in Section 4.3. 4.2 The Phases of Design Automation Before ....
J. Lienig. A Parallel Genetic Algorithm for Performance-Driven VLSI Routing. IEEE Transactions on Evolutionary Computation, 1(1):29--39, 1997. Bibliography 152
An Indexed Bibliography of Distributed Genetic Algorithms - Alander (1999) (4 citations) (Correct)
....IEE Proceedings, Control Theory and Applications, 223] IEEE Expert, 189, 251] IEEE Transactions on Circuits and Systems II, Analog Digit. Signal Process. 202] IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 379] IEEE Transactions on Evolutionary Computing, [340] IEEE Transactions on Fuzzy Systems, 288] IEEE Transactions on Neural Networks, 97] IEEE Transactions on Parallel and Distributed Systems, 64] IEEE Transactions on Power Systems, 245, 542] IEEE Transactions on Systems, Man, and Cybernetics, 130] IEICE Transactions on Fundamentals of ....
....S. 345] Lam, S. L. Y. 291] Lamont, Gary B. 111, 439] Laszewski, Gregor von, 446] Lawrence, P. D. 121] Lee, C. D. 500] Lee, Jongsoo, 206, 286] Lehndert, R. van, 498] Leuze, Michael R. 468, 469, 470] Levi, Paul, 342] Levine, David Mark, 104, 138] Li, T. 501] Lienig, Jens, [292, 305, 318, 340] Authors 17 Liepins, Gunar E. 432, 433] Lin, G. 168] Lin, Guangming, 247] Lin, S. C. 341] Lin, Shyh Chang, 189] Lindgren, Kristian, 43] Linkens, Derek. A. 434] Lipsitch, Marc, 44] Lishan, Kang, 65] Liu, Luoping, 87] Logar, Antonette M. 396] Lohrmann, Hartmut, 105] Lopes, ....
[Article contains additional citation context not shown here]
Jens Lienig. A parallel genetic algorithm for performance-driven VLSI routing. IEEE Transactions on Evolutionary Computing, 1(1):29-39, 1997. yEEA71879/97 ga97bLienig.
An Indexed Bibliography of Genetic Algorithms in Electronics and.. - Alander (1999) (1 citation) (Correct)
.... Design of Integrated Circuits, 248] IEEE Transactions on Computer Aided Design, 294, 302, 308, 323] IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 163, 165, 244, 299, 313, 330] IEEE Transactions on Computing, 205] IEEE Transactions on Evolutionary Computing, [280] IEEE Transactions on Industrial Electronics, 66] IEEE Transactions on Semiconductor Manufacturing, 222, 97] IEEE Transactions on Systems, Man, and Cybernetics, 160] IEEE Transactions on Very Large Scale Integration VLSI Systems, 220] IEICE Transactions on Fundamentals of Electronics ....
....P. 211] Lavenier, Dominique, 214] Lee, K. L. 40] Lee, Michael A. 270] Lee, Terry, 180, 229] Lee, Yuh Sheng, 163] Leenaerts, Domine, 30, 38] Lemoine, Eric, 39] Lesniak, Joanna, 18] Leu, Ming C. 114, 115] Leung, S. H. 149] Levitt, Jeremy R. 170] Liao, Jianmin, 70] Lienig, Jens, [131, 20, 157, 212, 241, 254, 269, 280] Lim, H. T. 40] Lin, Y. L. 301, 302] Lin, Youn Long, 163] Authors 15 Liu, B. D. 332] Liu, Luoping, 126] Liu, Xingzhao, 138, 11, 329, 118, 119, 120] Lohn, Jason, 101] Luchian, Henri, 13] Ly, Tai A. 330] Majhi, A. K. 171] Makki, R. Z. 133] Malgeri, M. 183] Mandal, C. A. ....
[Article contains additional citation context not shown here]
Jens Lienig. A parallel genetic algorithm for performance-driven VLSI routing. IEEE Transactions on Evolutionary Computing, 1(1):29--39, 1997. yEEA71879/97 ga97bLienig.
Evolutionary Algorithms for the Physical Design of VLSI.. - Cohoon, Karro, Lienig Self-citation (Lienig) (Correct)
....Subsequently, these extensions are reduced with the goal of reaching the xed size of the switchbox. While more costly in runtime, on numerous benchmark examples the genetic algorithm produces solutions with equal or better routing characteristics than the previously best published results. [Lienig (1997)] presents a parallel genetic algorithm for the channel and switchblock routing problem. The problem is based on the theory of punctuated equilibria from [Eldrege and Gould (1972) and [Cohoon et al. 1991) A genetic algorithm with punctuated equilibria is a parallel genetic algorithm in which ....
Lienig J., A Parallel Genetic Algorithm for Performance-Driven VLSI Routing, IEEE Trans. on Evolutionary Computation, vol. 1, no. 1,
Hybrid Genetic Algorithm for VLSI Macro Cell Layout - Sathiamoorthy.. (Correct)
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Lienig J. (1997) A Parallel Genetic Algorithm for Performance Driven VLSI Routing. IEEE Transactions on Evolutionary Computation Vol. I. No.1 :29-39
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