A. K. Uht, V. Sindagi, and S. Somanathan, "Branch Effect Reduction Techniques," IEEE COMPUTER, vol. 30, no. 5, pp. 71-81, May 1997.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....FP benchmarks over a 2 level adaptive branch predictor. The average number of branch penalty cycles per instruction for DBD reduces to :0475 compared to :0835 for the 2 level branch predictor. 1 Introduction The instruction level parallel processors rely upon dynamic branch prediction techniques [11] to improve performance. Several attempts have been made in the recent years to improve the accuracy of branch prediction [3, 7, 12] These predictors try to adapt to the dynamic program behavior in order to improve their performance. With typical branch frequency of about 20 , the impact of ....

A. K. Uht, V. Sindagi, and S. Somanathan, "Branch Effect Reduction Techniques," Computer, pp. 71-81, May 1997.

....This study builds on previous work in conditional branch prediction. Many alternative implementations were conceived by adapting existing conditional branch prediction architectures to indirect branches. The literature on conditional branch prediction is extensive. We refer to Uht et al. [123] for a recent general overview, and limit the discussion to work which is closely related to this study. 10.2.2.1 Basic prediction Yeh and Patt first proposed two level branch prediction [134] and presented a thorough classification [135] of two level predictors, which influenced the work ....

Augustus K. Uht, Vijay Sindagi, Sajee Somanathan. Branch Effect Reduction Techniques. IEEE Computer, May 1997.

....in order to effectively utilize available hardware resources. Control flow changes introduced by branches (conditional and unconditional, direct and indirect) disrupt the steady flow of instructions to the processor. Therefore, multiple issue execution is not able to exploit a high degree of ILP [1]. A branch predictor working at the instruction fetch pipeline stage can minimize the impact of control flow breaks by predicting the branch outcome and fetching instructions from the predicted path. Speculatively executed instructions must be discarded when a branch is mispredicted. High accuracy ....

A.K. Uht, V. Sindagi, and S. Somanathan. Branch Effects Reduction Techniques. IEEE Computer Magazine, 30(5):71--81, May 1997.

....Superscalar processor microarchitectures are particularly sensitive to control flow changes. Branches (conditional or unconditional, direct or indirect) can interrupt the steady flow of instructions to the processor pipeline, reducing the benefits that superscalar execution can afford [1]. Utilizing a branch predictor which works at instruction fetch time can minimize the impact of control flow breaks by predicting the branch 1 outcome and fetching instructions from the predicted path. Speculatively executed instructions must be discarded when a branch is mispredicted. Therefore ....

....sequential address and the other is usually encoded in the instruction itself. Therefore, the major goal becomes to predict the direction of the branch. A plethora of predictors have appeared in the literature, achieving very high prediction ratios (more than 95 for the SPEC 95 benchmark suite [1]) Unconditional direct branches are the easiest to predict since they are always taken and their address is encoded in the instruction. Our work here is focused on the correct prediction of unconditional indirect branches. Although their direction is already known (always taken) they can ....

A.K. Uht, V. Sindagi, and S. Somanathan. Branch Effects Reduction Techniques. IEEE Computer Magazine, 30(5):71--81, May 1997.

....and showed that a path based predictor with two bit partial addresses attained prediction rates similar to a patternbased predictor with taken not taken bits (for similar hardware budgets) Many alternative implementations in this study were inspired by conditional branch predictors. We refer to [USS97] for a recent general overview, to [YP93] for a classification of two level predictors, and [ECP96] for recent hybrid prediction results. 1 We were unable to obtain the exact benchmark inputs used by Chang et al. 21 Technical Report TRCS97 19: Accurate Indirect Branch Prediction 8. ....

Augustus K. Uht, Vijay Sindagi, Sajee Somanathan. Branch Effect Reduction Techniques. IEEE Computer, May 1997.

....Superscalar processor microarchitectures are particularly sensitive to control flow changes. Branches (conditional or unconditional, direct or indirect) can interrupt the steady flow of instructions to the processor pipeline, reducing the benefits that superscalar execution can afford [1]. Utilizing a branch predictor which works at instruction fetch time can minimize the impact of control flow breaks by predicting the branch outcome and fetching instructions from the predicted path. Speculatively executed instructions must be discarded when a branch is mispredicted. Therefore the ....

....sequential address and the other is usually encoded in the instruction itself. Therefore, the major goal becomes to predict the direction of the branch. A plethora of predictors have appeared in the literature, achieving very high prediction ratios (more than 95 for the SPEC 95 benchmark suite [1]) Unconditional direct branches are the easiest to predict since they are always taken and their address is encoded in the instruction. Our work here is focused on the correct prediction of unconditional indirect branches. Although their direction is already known (always taken) they can ....

A.K. Uht, V. Sindagi, and S. Somanathan. Branch Effects Reduction Techniques. IEEE Computer Magazine, 30(5):71--81, May 1997. 14

....branches and showed that a path based predictor with two bit partial addresses attained prediction rates similar to a patternbased predictor with taken not taken bits (for similar hardware budgets) Many predictors in this study were inspired by conditional branch predictors. We refer to [USS97] for a recent general overview, to [YP93] for the classification of two level predictors used in this paper, and [ECP96] for recent hybrid prediction results. 7. Conclusions and future work We have explored the limits of predictability of indirect branches. The results show that there is a large ....

Augustus K. Uht, Vijay Sindagi, Sajee Somanathan. Branch Effect Reduction Techniques. IEEE Computer, May 1997.

....in order to effectively utilize available hardware resources. Control flow changes introduced by branches (conditional and unconditional, direct and indirect) disrupt the steady flow of instructions to the processor. Therefore, multiple issue execution is not able to exploit a high degree of ILP [1]. A branch predictor working at instruction fetch time can minimize the impact of control flow breaks by predicting the branch outcome and fetching instructions from the predicted path. Speculatively executed instructions must be discarded when a branch is mispredicted. Therefore the accuracy of ....

A.K. Uht, V. Sindagi, and S. Somanathan. Branch Effects Reduction Techniques. IEEE Computer Magazine, 30(5):71--81, May 1997.

.... the net resulting IPC (Instructions Per Cycle) is always low (in the low single digits) There are several contributing factors to these disappointing results: many processors do not take advantage of the most sophisticated ILP techniques, e.g. only using simple single path branch speculation[21] to reduce the effects of unpredictable control flow; until recently, chip transistor budgets were not great enough to allow sophisticated ILP techniques to be realized; even with more transistors available, the existing hardware ILP extraction methods do not scale well either with increasing ....

.... of this statement, instructions within the domain have their predicates: I p pbc = which is clearly correct, while instructions after the domain have predicates: 1 I p pcpbcbc = that is, these instructions will execute regardless of the branch condition and are control independent[19, 21] of the branch, as expected. 40 p I 30 20 10 1 p in cp in p out cp out p 0 p 0 p 0 p 10 p 10 p 10 0 0 0 0 cp 10 p = p cp 40 10 10 p = p 10 0 bc cp = bc p 10 0 1 = bc p 0 bc p = p 00 bc p 0 bc p 0 = p = p out 0 d = e f if goto 40 bc x = y z u = v w r = s t ....

A. K. Uht, V. Sindagi, and S. Somanathan, "Branch Effect Reduction Techniques," IEEE COMPUTER, vol. 30, no. 5, pp. 71-81, May 1997.

....and branch predictor accuracy are modeled and studied. This work was supported in part by the Intel Corporation. This paper has been submitted for publication to the 30th International Symposium on Microarchitecture (Dec. 1997) Versions of Figures 1 and 2 have previously appeared in [15] and [16]. 1 1 Introduction and Background Many Branch Effect Reduction Techniques, or BERTs, have been proposed to increase the amount of Instruction Level Parallelism (ILP) exploitable by uniprocessors[16] One promising BERT is Disjoint Eager Execution (DEE) proposed and studied in [15] Although ....

....Microarchitecture (Dec. 1997) Versions of Figures 1 and 2 have previously appeared in [15] and [16] 1 1 Introduction and Background Many Branch Effect Reduction Techniques, or BERTs, have been proposed to increase the amount of Instruction Level Parallelism (ILP) exploitable by uniprocessors[16]. One promising BERT is Disjoint Eager Execution (DEE) proposed and studied in [15] Although common BERTs realize ILPs of factors of about 2 to 3 (performance speedup over sequential code) one version of DEE (DEE CD MF: DEE combined with minimal control dependencies) is claimed to realize ILP ....

A. K. Uht, V. Sindagi, and S. Somanathan. Branch Effect Reduction Techniques. COMPUTER, 30(5):71--81, May 1997.

....processors, such as Intel x86 microprocessors, Instruction Level Parallelism (ILP) must be exploited. ILP involves the execution of machine instructions in parallel. It is fine grain, occurring within an iteration of a loop, for example. In order to enhance ILP, many methods are commonly used[12], such as data dependency reduction and branch prediction. In the latter, when a CPU encounters a branch, it uses special hardware that predicts whether the branch will be taken or not taken (its sign) based on the branch s prior execution history; execution then proceeds down (just) the ....

....PE s. Each PE will likely have one SBlock associated with it. 6 Comparison to Other Work Virtually all commercial and most research superscalar machines use only simple SP execution with minimal register data dependencies[4] VLIW and other software based machines are an alternate approach; see [12] for a discussion and comparison of these and other methods. The multiscalar architecture[5] realizes concurrently executing tasks in multiple localities of SP executions. The realization of concurrent localities is a type of reduced control dependencies, originally devised in [6] and improved ....

A. K. Uht, V. Sindagi, and S. Somanathan. Branch Effect Reduction Techniques. COMPUTER, 30(5):71--81, May 1997.

....2. Many editorial changes were made. All of the Figures are unchanged; all of the Tables are new. The original version of this paper was submitted for publication to the 30th International Symposium on Microarchitecture (Dec. 1997) Versions of Figures 1 and 2 have previously appeared in [20] and [21]. 1 1 Introduction and Background Many Branch Effect Reduction Techniques, or BERTs, have been proposed to increase the amount of Instruction Level Parallelism (ILP) exploitable by uniprocessors[21] One promising BERT is Disjoint Eager Execution (DEE) proposed and studied in [20] Although ....

....Microarchitecture (Dec. 1997) Versions of Figures 1 and 2 have previously appeared in [20] and [21] 1 1 Introduction and Background Many Branch Effect Reduction Techniques, or BERTs, have been proposed to increase the amount of Instruction Level Parallelism (ILP) exploitable by uniprocessors[21]. One promising BERT is Disjoint Eager Execution (DEE) proposed and studied in [20] Although common BERTs realize ILPs of factors of about 2 to 3 (performance speedup over sequential code) one version of DEE (DEE CD MF: DEE combined with minimal control dependencies) is claimed to realize ILP ....

A. K. Uht, V. Sindagi, and S. Somanathan. Branch Effect Reduction Techniques. COMPUTER, 30(5):71--81, May 1997.

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A. K. Uht, V. Sindagi, and S. Somanathan, "Branch Effect Reduction Techniques," COMPUTER, May 1997.

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Augustus K. Uht, Vijay Sindagi, Sajee Somanathan. Branch Effect Reduction Techniques. IEEE Computer, May 1997.

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Augustus K. Uht, Vijay Sindagi, Sajee Somanathan. Branch Effect Reduction Techniques. IEEE Computer, May 1997.

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Augustus K. Uht, Vijay Sindagi, Sajee Somanathan. Branch Effect Reduction Techniques. IEEE Computer, May 1997.

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