Andrew Chang. VLSI datapath choices: Cell-based versus full-custom. Master's thesis, MIT, 1998. Home/Search Document Details and Download
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Closing the Gap Between ASIC and Custom: An ASIC Perspective - Chinnery, Keutzer (2000) (6 citations) (Correct)
....are not automatically invoked in register transfer level logic synthesis of ASICs. Use of these predefined macro cells for an ASIC can significantly improve the resulting design, by reducing the number of logic levels for implementing complex logic functions and reducing the area taken up by logic[5]. 5. FLOORPLANNING, PLACEMENT, AND ROUTING Wire delays associated with global wires between physical modules can be a dominant portion of the total path delay. The delay associated with wires depends on the length of the wire, the width and aspect ratios of the wire, and on proper driving of ....
....to identify similar structures that may be abutted or placed next to each other appropriately will reduce area, reducing wire lengths and increasing performance. A bit slice may be laid out automatically then tiled, rather than the circuitry being placed without considering that it may be abutted[5]. Regular data paths can be best laid out by hand or tiling slices for abutment, but custom design is not as effective with irregular structures. 6. CIRCUITS, TRANSISTOR AND WIRE SIZING In an ideal design, each circuit is optimally crafted from transistors and each transistor is individually ....
Chang, A. VLSI Datapath Choices: Cell-Based Versus Full-Custom", SM Thesis, Massachusetts Institute of Technology, February 1998. ftp://cva.stanford.edu/ pub/publications/achang_masterworks980427.pdf
The Role of Custom Design in ASIC Chips - Dally, Chang (2000) (12 citations) (Correct)
....cell. Finally, for very special cases, custom circuits are employed within the cell. Our experience shows that the level of effort to develop a crafted cell, including generating all of the views needed to support the standard cell tools, is quite low (0. 5 4 person days depending on complexity) [1][6] and that a very small number of cells (10 20) is sufficient to realize most datapaths. Moreover these cells are reusable. They really should already be in the library. An orthogonal step, that can be applied independent of tiling or crafted cells, is to use signaling circuits to improve the ....
....tiling logic into the cells of a datapath. Datapath tiling can be exploited at several levels of customization. The impact on area and delay of different design styles is shown in Figure 3 and Table 1. These results are from four implementations of a 64 bit microprocessor register fetch stage [1][6] This datapath includes a 7 ported 75 entry 64 bit register file, a six entry reservation station, bypass multiplexors, 18 bit immediate insertion logic and thirteen 1 bit condition code registers. The baseline custom design is implemented in IBM s CMOS5L (Leff = 0.5m, M2 M3 pitch 1.8m) and ....
CHANG, ANDREW, VLSI Datapath Choices: Cell-Based Versus FullCustom, SM Thesis, Massachusetts Institute of Technology, February 1998.
The VLSI Implementation and Evaluation of Area- and.. - Khailany (2003) (5 citations) (Correct)
No context found.
Andrew Chang. VLSI datapath choices: Cell-based versus full-custom. Master's thesis, MIT, 1998.
The VLSI Implementation and Evaluation of Area- and.. - Khailany (2003) (5 citations) (Correct)
No context found.
Andrew Chang. VLSI datapath choices: Cell-based versus full-custom. Master's thesis, MIT, 1998.
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