B. Black and J. Shen. Scalable register renaming via the quack register file. Technical Report CMuArt 00-1, Carnegie Mellon University, April 2000. Home/Search Document Details and Download
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Half-Price Architecture - Kim, Lipasti (2003) (1 citation) (Correct)
....high performance microprocessor requires a register file with many read and write ports. This highly multiported structure becomes challenging to design because the area of a register file increases quadratically and the latency increases approximately linearly as the number of ports grows [6][7] 8] Conventional register files in RISC style microprocessors have two register read ports and one write port per issue slot. Even though this 2X read port configuration guarantees register accesses for all types of instructions, it 1. The wakeup bus length and the number of tag comparators ....
B. Black and J.P. Shen, Scalable register renaming via the Quack register file, Tech report, CMuART-2000-01, Carnegie Mellon University, Pittsburgh, 2000.
Turboscalar: A High Frequency High IPC Microarchitecture - Bryan Black And (2000) (2 citations) Self-citation (Black Shen) (Correct)
....hot pipeline is performed in the optimizing back end, during trace construction, using the new TMP multiple branch predictor [13] as discussed in Section4.3. Given the shallow hot pipeline of the Turboscalar, a new fast single cycle register file is required. The Quack register file, proposed in [2], provides three key ingredients to the Turboscalar implementation. First it utilizes a virtual rename tag that can be generated in the back end, requiring no renaming in the front end of the machine. Second, it has a high frequency read that is independent of the physical rename register count ....
....that is independent of the physical rename register count and instruction dispatch width. Third, fewer read and write ports are required by the Quack register file than more traditional implementations, further facilitating source operand read for a large number of instructions in a single cycle. [2] analyzes the latency of the Quack register file for a 0.18um process, and demonstrates that source operand read for 24 instructions can be performed in a single cycle. The Quack register file organization is illustrated in Figure5. Extensive details of the Quack register file are documented in ....
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B. Black and J. Shen, "Scalable Register Renaming via the Quack Register File" Technical Report CMuArt 00-1, Carnegie Mellon University, April 2000.
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B. Black and J. Shen. Scalable register renaming via the quack register file. Technical Report CMuArt 00-1, Carnegie Mellon University, April 2000.
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B. Black and J. Shen. Scalable Register Renaming via the Quack Register File. Technical Report CMuArt 00-1, Carnegie Mellon University, April 2000.
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B. Black, J. P. Shen - "Scalable Register Renaming via the Quack Register File" -- Technical Report CMuART-2000-01
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B. Black and J. Shen. Scalable Register Renaming via the Quack Register File. Technical Report CMuArt 00-1, Carnegie Mellon University, April 2000.
A Large, Fast Instruction Window for Tolerating Cache.. - Lebeck, Koppanalil.. (Correct)
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B. Black and J. Shen. Scalable Register Renaming via the Quack Register File. Technical Report CMuArt 00-1, Carnegie Mellon University, April 2000.
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