GARSIDE,J.D.,TEMPLE,S.,AND MEHRA,R. 1996. The AMULET2e cache system. In 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....fixed clock rate, or the design may have a large area overhead to handle worst case computation efficiently. Recently, a number of asynchronous chips have been successfully designed and or fabricated, both for microprocessors and DSPs [21, 11, 14, 15, 16, 26] including embedded processors [6, 7, 8]. Several of these designs have demonstrated the benefits of asynchronous design for average case operation. 1 In this paper, we propose a new architecture an implementation of an asynchronous Hu#man decoder. The design uses an entirely new organization, and is 83 faster than our earlier design ....

J.D. Garside, S. Temple, and R. Mehra. The amulet2e cache system. In Async96 Symposium. ACM, April 1996.

....Constraint The design of the matched delays is an important problem. A simple approach is to use an inverter chain as a rough matched delay. A better approach used in highperformance systems, where tight margins are critical, is to use a replicated portion of the critical path as the delay (see [19, 32, 65]) In CMOS implementations, delays depend heavily on the sizes of transistors and their loading, and also on the final routing and placement of modules, so safety margins are required for correct operation. A potential weakness of the use of single rail systems is that the bundled delays match ....

....this case, our system may be up to 40 faster (see Section 3.6) Delay Matching. In high performance single rail datapaths, tight margins in delay matching are necessary. Matched delays that accurately model the logic are 58 usually built by using a single extracted portion of the critical path [19, 32, 65], with similar layout and loading. However, this approach is not directly applicable to half matched delays in TFP, which may therefore require larger safety margins, thus degrading performance. 3.6 Results In this section, we present the results of detailed comparisons of the characteristics of ....

J. D. Garside, S. Temple, and R. Mehra. The AMULET2e cache system. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 208--217. IEEE Computer Society Press, March 1996.

....so the RAM will be configured to take one reference delay. The ROM, which is typically much slower, may be configured to take several reference delays. Note that the reference delay is only used for off chip timing; all on chip delays are self timed. 4.2. AMULET2e cache The write through cache [14] comprises four 1 Kbyte blocks, each of which is a fully associative random replacement store with a quad word line and block size. Two address lines select which of the four blocks is used for a particular access. A pipeline register between the CAM and the RAM sections allows a following access ....

J. D. Garside, S. Temple and R. Mehra, The AMULET2e Cache System, Proc. Async'96, Aizu-Wakamatsu, Japan, March 18-21 1996.

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GARSIDE,J.D.,TEMPLE,S.,AND MEHRA,R. 1996. The AMULET2e cache system. In 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems.

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