Carole Dulong, Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel Lavery, Wei Li, John Ng, and David Sehr. An Overview of the Intel IA-64 Compiler. Intel Technology Journal, (Q4), 1999. Home/Search Document Details and Download
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Architecture for a Next-Generation GCC - Lattner, Adve (2003) (Correct)
....and 1.2s for the 255.vortex programs, which are about 136,000 and 67,000 lines of C code respectively [13] Other simpler algorithms may obviously run much more quickly. 5 Related Work There is a vast amount of related work on interprocedural optimization in research and commercial compilers [1, 8, 2, 9, 3]. To avoid major changes to the build process, all of these compilers combine the program together at link time in a very high level representation, before any substantial optimization is performed. Most often, this representation takes the form of the source language Abstract Syntax Tree (AST) ....
C. Dulong, R. Krishnaiyer, D. Kulkarni, D. Lavery, W. Li, J. Ng, and D. Sehr. An overview of the Intel IA-64 compiler. Intel Technology Journal, (Q4), 1999.
Code Compression Techniques for Embedded Systems - Nyström, Runeson, Sjödin (Correct)
....gives best results if the compiler has access to the whole program. Thus, it desirable to abandon the traditional framework in which modules are compiled independently, and instead give the compiler access to information from all modules. Current trends in optimizing compilers (see for example [5]) suggest that future compilers will rely on inter procedural (whole program) techniques for many optimizations, so it is reasonable to assume that the necessary infrastructure for applying code compression at the intermediate code level will be available. 2 Related Work Algorithms for code ....
Carole Dulong, Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel Lavery, Wei Li, John Ng, and David Sehr. An overview of the Intel IA-64 compiler. Intel Technology Journal, November 1999.
Incorporating Cache Models in Iterative Compilation.. - Kisuki, Knijnenburg.. (2000) (Correct)
....available on a chip 1 . This represents an opportunity and challenge to computer architects to design and build processors capable of exploiting such a resource. Increasingly, processors rely on compiler technology to exploit the potential resources by carefully mapping applications to hardware [8]. However, the rate of architectural change is such that in the near future it will not be possible to produce high performance optimizing compilers in the time available and we therefore need to consider adaptive compilers, i.e. those that are able to cope with a changing hardware platform ....
C. Dulong, R. Krishnaiyer, D. Kulkarni, D. Lavery, W. Li, J. Ng, and D. Sehr. An overview of the Intel IA-64 compiler. Intel Tecnology Journal, Q4, 1999.
Super Scalar Sample Sort - Sanders, Winkel (2004) (1 citation) (Correct)
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Carole Dulong, Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel Lavery, Wei Li, John Ng, and David Sehr. An Overview of the Intel IA-64 Compiler. Intel Technology Journal, (Q4), 1999.
Inter-Iteration Scalar Replacement in the Presence of - Conditional Control-Flow Mihai (2004) (Correct)
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Carole Dulong, Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel Lavery, Wei Li, John Ng, and David Sehr. An overview of the Intel IA-64 compiler. Intel Technology Journal, 1999.
Annotations for Portable Intermediate Languages - Reig (2001) (6 citations) (Correct)
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Carole Dulong, Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel Lavery, Wei Li, John Ng, and David Sehr. An overview of the Intel IA-64 compiler. Intel Technology Journal, (Q4), 1999.
Inter-Iteration Scalar Replacement in the Presence of - Conditional Control-Flow Mihai (Correct)
No context found.
Carole Dulong, Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel Lavery, Wei Li, John Ng, and David Sehr. An overview of the Intel IA-64 compiler. Intel Technology Journal, 1999.
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