OpenCAD V 5.2 Users Manual. NEC Electronics, Inc., Jan. 1999.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....accuracy of macro modeling based RTL power estimation is very high, when compared to gate level power estimation. For example, the RTL power estimate for CKT3 differs by only 6:44 from the corresponding gate level power estimate. Gate level power estimation was performed by the OPENCAD tool suite [32] on a gate level netlist obtained after technology mapping (with the CB12L cell library [30] and synthesis using Synopsys Design Compiler [33] We also compared the performance of our techniques with conventional methods such as test bench reduction and statistical sampling. Figure 9(a) plots ....

OpenCAD V 5.2 Users Manual. NEC Electronics, Inc., Jan. 1999.

.... tool, CYBER [18] and logic synthesis using Synopsys Design Compiler [19] With a designer specified input trace and the technology mapped logic netlist generated after synthesis, we evaluated the area, energy and performance of the system, using in house tools from a commercial design flow [20]. In this example, we report the execution time (product of the clock period and number of clock cycles) which is 2,628 ns under the first resource budget. The second resource budget, which corresponds to the third column in Figure 2(b) shows another resource allocation for P1, P2 and P3, under ....

....were subjected to high level synthesis using a state of the art commercial tool, CYBER [18] with and without the techniques presented in this paper, logic synthesis was performed using Synopsys Design Compiler [19] and the resultant circuits were mapped to NEC s 0. 35 cell based array library [20]. The gate level circuits were compared with respect to the following metrics: area, performance, and energy. These metrics were extracted from the technology mapped circuits and designer provided test benches using in house tools from a commercial design flow [20] The results obtained are ....

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OpenCAD V 5 Users Manual. NEC Electronics, Inc., Sept. 1997.

....as the original, variable latency, and reduced variable latency RTL implementations, respectively. For each design, the expected number of clock cycles (ENC) metric, computed as described in [7] was used to compare the performance of the RTL implementations. The logic synthesis tool VARCHSYN [12] was used to perform logic optimizations and to technology map the circuits to the NEC CMOS6 technology library. The area estimates reported here represent the cell area (grid count) usage information from the technology library. While we do not explicitly target power reduction in the techniques ....

....traded off for further reductions in power consumption through supply voltage scaling [13] We performed experiments to evaluate the power efficiency of variable latency optimized designs. Power estimation was performed through simulation using typical input sequences with NEC s inhouse tool, CSIM [12]. Supply voltage scaling was performed using the equation V dd initial #V dd initial,V t # 2 # T orig = V dd new #V dd new,V t # 2 # T opt where V dd initial is the initial supply voltage, V dd new is the new supply voltage, and V t is the threshold voltage for the chosen technology. The ....

OpenCAD V 5 Users Manual. NEC Electronics, Inc., Sep. 1997.

....from the high level synthesis tool 2. The resulting RTL implementations were synthesized using Synop sys Design Compiler [ 17] and mapped to NEC s 0. 35 micron gate array technology [18] Gate level power estimation was performed using an in house tool that is used commercially for sign off [19] (the power estimation process includes estimated interconnect and clock network parasiacs) Figures 1Co) f) present the cycle by cycle power consumption profiles of five distinct designs that implement the behavior resfl. Each profile represents the cycle by cycle power variation over 100 clock ....

....obtained through the use of the proposed techniques. Power estimation was performed through simulation using input sequences that were specified for functional verification (i.e. they provide high behavioral and RTL code and value Coverage) NEC s in house gate level power estimation tool [19] was used to generate a cycle by cycle report, which was post processed to Compute the peak power as well as the peak power differential. We evaluated the proposed technique using ten example benchmarks. Example Poly represents the Computation of a polynomial. PPsum is a parallel prefix sum ....

OpenCAD V5 Users Manual, NEC Electronics, Inc., Sep. 1997.

....(a) optimized behavioral description, b) optimized CDFG, and (c) optimized STG 9 when the input sub space condition is satisfied. We implemented the original and optimized versions of the Wavelet example using a state of the art commercial high level synthesis and logic synthesis design flow [21], and evaluated their performance and energy consumption after mapping them to a 0:35 micron cell based array technology [21] Identical resource constraints and synthesis scripts were used in order to isolate the benefits of input space adaptive design. Figures 2(c) and 3(c) show the schedules ....

....satisfied. We implemented the original and optimized versions of the Wavelet example using a state of the art commercial high level synthesis and logic synthesis design flow [21] and evaluated their performance and energy consumption after mapping them to a 0:35 micron cell based array technology [21]. Identical resource constraints and synthesis scripts were used in order to isolate the benefits of input space adaptive design. Figures 2(c) and 3(c) show the schedules generated for the original and optimized versions of the Wavelet example, respectively, as state transition graphs (STGs) As ....

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OpenCAD V 5 Users Manual. NEC Electronics, Inc., Sept. 1997.

....for all the circuits. Then, we generated an independent set of 10000 vectors and used it to simulate all the 7 circuits. For each circuit, we measured the following three quantities for each vector: the actual power dissipated (estimated using the NEC OpenCAD cell based power estimator [16]) the power value estimated by macro Gamma model conventional , and the power estimated by macro Gamma model proposed . By substituting these three quantities in the formula for Absolute Cycle by cycle Error (ACE) we computed the estimation error of the macro Gamma model conventional and the ....

OpenCAD V 5 Users Manual. NEC Electronics, Inc. 1997.

....and the most promising common case was chosen for synthesis. The original circuits were modified by adding common case detection and execution circuitry. The original and power optimized RTL descriptions were mapped to gate level netlists using synthesis tools from the NEC CAD tool suite, OpenCAD [15]. The resulting gatelevel circuits were compared with respect to the following metrics: area, performance, and power. The area, delay, and power consumption were extracted from technology mapped gate level circuits using static timing analysis tools and power estimation tools from the NEC OpenCAD ....

....resulting gatelevel circuits were compared with respect to the following metrics: area, performance, and power. The area, delay, and power consumption were extracted from technology mapped gate level circuits using static timing analysis tools and power estimation tools from the NEC OpenCAD suite [15]. The results obtained are summarized in Tables 1 and 2. The power consumption of the original and the optimized designs are computed in the following manner when V dd scaling is not performed. For the original design, the energy, E orig , consumed while executing the input trace is divided by ....

OpenCAD V 5 Users Manual, NEC Electronics, Inc., Sept. 1997.

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