Gerd Behrmann, Kim G. Larsen, Justin Pearson, Carsten Weise, and Wang Yi. E#cient Timed Reachability Analysis Using Clock Di#erence Diagrams. In Proc. 11th International Conference on Computer Aided Verification (CAV'99), vol. 1633 of Lecture Notes in Computer Science, pp. 341--353. Springer, 1999.  Home/Search   Document Not in Database   Summary   Related Articles   Check

.... representing larger equivalence classes using convex hulls [16] These can be represented in di#erence bound matrices (DBMs) 16] since they represent allowed separations in a system, and many e#cient algorithms have been developed to manipulate DBMs [17] DBMs can also be implicitly represented [18, 19]. A zone implicitly represents an allowed execution trace in the circuit. A di#erent ordering on a set of concurrent transitions can lead to a di#erent zone. This creates an exponential branching in the timed state space. As the zone is a partially ordered set relating various transition times, ....

G. Behrmann, K. Larsen, J. Pearson, C. Weise, and W. Yi. E#cient timed reachability analysis using clock di#erence diagrams. In International Conf. on Computer Aided Verification, volume 1633 of Lecture Notes in Computer Science. SpringerVerlag, July 1999.

....they don t even include addition) many proof obligations in hardware and software verification can be stated in these logics. In [22] Pratt already noticed the relevance of separation formulas of the form x y c. A similar fragment is also used in real time model checking as in Uppaal [6, 5]. Propositional logic with equality and uninterpreted functions (EUF) has been proposed for verifying correctness of hardware designs [12] Also the techniques of [11] are applied to proving equivalence of hardware designs. In [20] similar techniques are applied to the verification of the ....

G. Behrmann, K. G. Larsen, J. Pearson, C. Weise, and W. Yi. E#cient timed reachability analysis using clock di#erence diagrams. In Proc. of 11th Computer Aided Verification, pages 341--353, 1999.

....that explicitly enumerate the discrete component of the state space. Kronos uses Di#erence Bound Matrices (DBMs) as the symbolic representation [19] of the infinite component. Uppaal2k uses, in addition, Clock Di#erence Diagrams (CDDs) to symbolically represent unions of convex clock regions [6]. In a CDD, a node is labeled by the di#erence of a pair of clock variables, and each outgoing edge from a node is labeled with an interval bounding that di#erence. Note that while Kronos can check arbitrary TCTL formulas, Uppaal2k is limited to checking reachability properties and very restricted ....

Gerd Behrmann, Kim Guldstrand Larsen, Justin Pearson, Carsten Weise, and Wang Yi. E#- cient timed reachability analysis using clock di#erence diagrams. In N. Halbwachs and D. Peled, editors, Computer-Aided Verification, volume 1633 of Lecture Notes in Computer Science, pages 341--353. Springer-Verlag, July 1999.

....particular they don t even include addition) many proof obligations in hardware and software verification can be stated in these logics. In [22] Pratt already noticed the relevance of separation formulas of the form x y c. A similar fragment is also used in real time model checking as in Uppaal [6, 5]. Propositional logic with equality and uninterpreted functions (EUF) has been proposed for verifying correctness of hardware designs [12] Also the techniques of [11] are applied to proving equivalence of hardware designs. In [20] similar techniques are applied to the verification of the ....

G. Behrmann, K. G. Larsen, J. Pearson, C. Weise, and W. Yi. E#cient timed reachability analysis using clock di#erence diagrams. In Proc. of 11th Computer Aided Verification, pages 341--353, 1999.

....Uppaal additionally allows data variables and synchronization mechanisms to model communication between concurrent timed automata. It can analyze reachability properties and simple liveness properties. The timed automata are internally represented in a compact form using clock di#erence diagrams [14]. Additional information about Uppaal can be found at www.docs.uu.se docs rtmv uppaal . Kronos is another tool for the analysis of timed automata. More information about Kronos can be found in [32] and online at www verimag.imag.fr TEMPORISE kronos. The tool HyTech analyzes a class of hybrid ....

G. Behrmann, K. Larsen, J. Pearson, C. Weise, and W. Yi. E#cient timed reachability analysis using clock di#erence diagrams. In Computer Aided Verification, 11th International Conference, volume 1633 of LNCS. Springer-Verlag, 1999.

....et al. 14] have described a data structure similar to DDDs called clock di erence diagrams (CDDs) however, they do not de ne an algorithm for eliminating quanti ers in a CDD, and the algorithm for determining satis ability of a CDD is di erent. CDDs have been implemented in the tool Uppaal [4]. The paper is organized as follows: Section 2 gives an overview of the Standard ML (SML) interface, Section 3 is a short introduction to the implementation, and Section 4 presents a model checker for real time systems written in SML. 2 Interface This section gives an overview of the SML ....

G. Behrmann, K.G. Larsen, J. Pearson, C. Weise, and W. Yi. Ecient timed reachability analysis using clock dierence diagrams. In Proc. 11th Conference on Computer Aided Verication, LNCS 1633, pages 341353, 1999.

....check in the line marked with ( we can use the algorithm in Fig. 1(a) immediately. Di erence decision diagrams [38] are a candidate for such a data structure which furthermore allows reuse of sub formula among the discrete states. Initial experiments with this approach implemented in Uppaal [6] show a signi cant improvement in memory consumption, even though the discrete states are still enumerated explicitly. In this chapter we address all three problems by constructing the set of reachable states R in a fully symbolic manner, without enumerating the discrete states and without ....

G. Behrmann, K.G. Larsen, J. Pearson, C. Weise, and W. Yi. Ecient timed reachability analysis using clock dierence diagrams. Technical Report 99/105, DoCS, Uppsala University, 1999.

....timing information (e.g. DBMs [33] However, the development of e cient data structures and techniques to handle at the same time both timing information and the state explosion problem has so far proved elusive. We expect, however, exciting developments on this line of research see, e.g. [16]. Acknowledgements Carsten Weise suggested the title of this paper, and gave useful suggestions on a draft of its extended abstract [4] Special thanks to Anders Ravn for his insightful comments and thorough proofreading. Many thanks to Philippe Schnoebelen for discussions about complexity and ....

G. Behrmann, K. Larsen, J. Pearson, C. Weise, and W. Yi, Ecient timed reachability analysis using clock dierence diagrams, in Proc. 11th Int. Conf. Computer Aided Verication (CAV'99), Trento, Italy, July

....not suited as a representation of the state space in tools. Therefore tools like Kronos [41] and Uppaal [109] are based on the notion of zones which are collections of regions. The two main ways of representing zones are Di#erence Bounded Matrices (DBMs) 60] and Clock Di#erence Diagrams (CDDs) [31] (also presented as Di#erence Decision Diagrams in [124] Both Kronos and Uppaal represent zones using DBMs, which have proven to be well suited for representing the state space of large systems. In Uppaal, zones can also be represented using CDDs but this has not been tested to the same extent ....

G. Behrmann, K. G. Larsen, J. Pearson, C. Weise, and W. Yi. E#cient timed reachability analysis using clock di#erence diagrams. In N. Halbwachs and D. Peled, editors, Proc. of the 11th Int. Conf. on Computer Aided Verification,

....continuous nature of the timed state space, but are too small to significantly reduce the number regions at a given state. Zones extend regions by representing larger equivalence classes using convex hulls [17] These can be explicitly or implicitly represented in di#erence bound matrices (DBMs) [18, 19]; and many e#cient algorithms have been developed to manipulate DBMs [20] A zone implicitly represents the ordering of transitions in the system. Thus, a di#erent interleaving of a set of independent transitions can lead to a different zone causing an exponential branching in the timed state ....

G. Behrmann, K. Larsen, J. Pearson, C. Weise, and W. Yi. E#cient timed reachability analysis using clock di#erence diagrams. In International Conf. on Computer Aided Verification, volume 1633 of Lecture Notes in Computer Science. Springer-Verlag, July 1999.

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G. Behrmann, K.G. Larsen, J. Pearson, C. Weise, and W. Yi. E#cient Timed Reachability Analysis Using Clock Di#erence Diagrams. Lecture Notes in Computer Science, 1633, 1999. In Proceedings of Computer Aided Verification 1999.

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Gerd Behrmann, Kim G. Larsen, Justin Pearson, Carsten Weise, and Wang Yi. E#cient Timed Reachability Analysis Using Clock Di#erence Diagrams. In Proc. 11th International Conference on Computer Aided Verification (CAV'99), vol. 1633 of Lecture Notes in Computer Science, pp. 341--353. Springer, 1999.

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Gerd Behrmann, Kim G. Larsen, Justin Pearson, Carsten Weise, and Wang Yi. E#- cient timed reachability analysis using clock di#erence diagrams. In Proc. CAV'99, LNCS 1633, pages 341--353. Springer, 1999.

No context found.

G. Behrmann, K. G. Larsen, J. Pearson, C. Weise, and W. Yi. E- cient timed reachability analysis using clock dierence diagrams. In 11th Computer-Aided Verication, Trento, Italy, July 1999.

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