T.G. Lang, J.T. O'Quin, and R.O. Simpson. Threaded code interpreter for object code. IBM Technical Disclosure Bulletin, pages 4238--4241, March 1986. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Talisman: Fast and Accurate Multicomputer Simulation - Bedichek (1995) (24 citations) (Correct)
....programs on hundreds of simulated processors. In addition, it had to model timing accurately. We could not afford to spend years constructing a complex simulator or waiting for results from a slow one. For these reasons, we wrote a simulator that translates instructions to threaded code [3, 14], which is then executed. The threaded code is cached, so that the price of translation for most instructions is paid just once, the first time they are encountered in the code stream. The result is a simulator that has a slow down of about 100 per simulated processor. Its timing is close enough ....
T.G. Lang, J.T. O'Quin, and R.O. Simpson. Threaded code interpreter for object code. IBM Technical Disclosure Bulletin, pages 4238--4241, March 1986.
Partial Translation - Magnusson (1993) (4 citations) (Correct)
....translating to an internal format and then interpreting this format. The traditional approach has been to bundle these phases into a single operation (Knuth 1973; Calingaert 1979) A more recent approach is to translate to an efficient internal format only once, and then interpret this format (Lang et#al. 1986; Bedichek 1990) Adopting May s terminology, we can call the former first generation simulators and the latter second generation simulators (May 1987) First generation simulators are mostly of historical interest. The early second generation simulators actually translated the target code to host ....
....The three alternatives are illustrated in figure 2. Incremental translation Translating individual instructions to native code brought the slowdown of simulators down to around 10, an improvement of one or two orders of magnitude over previous techniques. The method is quite straight forward (Lang et#al. 1986). A fixed memory expansion is allocated for the code to be executed, allowing fast address mapping. This memory space is initialised with subroutine calls to a translation routine. When program flow reaches such a cell, the target instruction is translated to one or more host instructions. If ....
Lang, T. G.; J. T. O'Quine; and R. O. Simpson. 1986. "Threaded Code Interpreter for Object Code." IBM Technical Disclosure Bulletin 28, no. 10 (March): 4238-4241.
The Meerkat Multicomputer: Tradeoffs in Multicomputer Architecture - Bedichek (1994) (6 citations) (Correct)
....programs on hundreds of simulated processors. In addition, it had to model timing accurately. We could not afford to spend years constructing a complex simulator or waiting for results from a slow one. For these reasons, we wrote a simulator that translates instructions to threaded code [11, 56], which is then executed. The threaded code is cached, so that the price of translation for most instructions is paid just once, the first time they are encountered in the code stream. The result is a simulator that has a slow down of about 100 per simulated processor. Its 50 timing is close ....
T.G. Lang, J.T. O'Quin, and R.O. Simpson. Threaded code interpreter for object code. IBM Technical Disclosure Bulletin, pages 4238--4241, March 1986.
Some Efficient Architecture Simulation Techniques - Bedichek (1990) (35 citations) (Correct)
....second generation simulator. We translate 88000 instructions to threaded code, while May does flow analysis and generates host instruction sequences with semantics that match the program being simulated. A scheme, similar to ours, for translating target instructions to threaded code is outlined in [4]. Other systems that translate instructions on the fly to a quick to execute form include the VAX 8800 series of computers [5] the CRISP microprocessor [6] and a Smalltalk 80 interpreter [7] When Tektronix engineers debug kernels and diagnostic programs on the hardware, they use a ....
Lang, T.G., O'Quin, J.T., and Simpson, R.O., "Threaded Code Interpreter for Object Code", IBM Technical Disclosure Bulletin, 4238-4241 (March 1986).
A Compact Intermediate Format for SIMICS - Peter Magnusson (1994) (3 citations) (Correct)
No context found.
Lang, T. G.; J. T. O'Quine; and R. O. Simpson. 1986. "Threaded Code Interpreter for Object Code." IBM Technical Disclosure Bulletin#28, no.#10 (March): 4238-4241.
Some Efficient Techniques for Simulating Memory - Peter Magnusson (1994) (2 citations) (Correct)
No context found.
Lang, T. G.; J. T. O'Quine; and R. O. Simpson. 1986. "Threaded Code Interpreter for Object Code." IBM Technical Disclosure Bulletin#28, no.#10 (March): 4238-4241.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC