D. Dill. Timing assumptions and verification of finite-state concurrent systems. In J. Sifakis, editor, Automatic Verification Methods for Finite-State Systems, LNCS Home/Search Document Not in Database Summary Related Articles Check |
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Sur La Verification De La Satisfaction Pour La Logique Des.. - Mahfoudh (2003) (Correct)
....presents some possible representations of conjunctions of di#erence constraints. It starts by the geometrical one, namely convex timed polyhedra, and focuses after on Di#erence Bound Matrices (or DBMs) which were first introduced by Bellman in [Bel57] and used for timing verification by Dill in [Dil89] 2.5.1 Convex timed polyhedra A convex timed polyhedron [BM00] is a polyhedron resulting from the finite intersection of half spaces. More formally, a convex timed polyhedron # is defined as follows: # = # 1 #m # #m # 1 . #m and # 1 , #m are hyper planes ....
D. L. Dill. Timing assumptions and verification of finite-state concurrent systems. In J. Sifakis, editor, Automatic Verification Methods for Finite State Systems, volume 407 of Lecture Notes in Computer Science, pages 197--212, 1989.
An Analyzer for Message - Sequence Charts Rajeev (Correct)
....The label [1; 2] on the edge from s 1 to r 1 specifies the lower and upper bounds on the delay of message delivery. The label [5; 6] on the vertical line from r 1 to s 2 specifies bounds on the delay between r 1 to s 2 , and models an assumption about the speed of process p 2 . The event set timer [1,2] [1,2] 4 [1,2] 5,6] set timer expire 1 p 2 p 1 FIGURE 5. An MSC with timing constraints corresponds to setting a timer which expires after 4 time units. The timing information, in this case, is consistent with the visual order of the two receive events expire and r 2 . In fact, we ....
....[1; 2] on the edge from s 1 to r 1 specifies the lower and upper bounds on the delay of message delivery. The label [5; 6] on the vertical line from r 1 to s 2 specifies bounds on the delay between r 1 to s 2 , and models an assumption about the speed of process p 2 . The event set timer [1,2] [1,2] 4 [1,2] 5,6] set timer expire 1 p 2 p 1 FIGURE 5. An MSC with timing constraints corresponds to setting a timer which expires after 4 time units. The timing information, in this case, is consistent with the visual order of the two receive events expire and r 2 . In fact, we can ....
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D.L. Dill. Timing assumptions and verification of finite-state concurrent systems. In Automatic Verification Methods for Finite State Systems, LNCS 407, pp. 197--212, 1989.
Verification of Timed Automata Based on Similarity - Dembinski, Penczek, Polrola (2002) (Correct)
....LTL) 10] The aim of our paper is to show that minimal model generation methods can be used not only for preserving bisimulation, but also for preserving a weaker relation like similarity. We know that similarity is induced by the universal fragment of CTL (i.e. ACTL [11] so preserves LTL [9], but it is still stronger than the trace equivalence. Since preserving the weaker relation results in generating smaller models, our approach constitutes another step towards reducing the unnecessary complexity of automated program verification. Our method is applied to improving the partitioning ....
Dill, D.: Timing Assumptions and Verification of Finite State Concurrent Systems, in: Automatic Verification Methods for Finite-State Systems, vol. 407 of LNCS, Springer-Verlag, 1989, 197 -- 212.
Improved POSET Timing Analysis in Timed Petri Nets - Eric Mercer University (2001) (Correct)
....unique region generated at an untimed state during the trace evolution. A region naturally address the continuous nature of the timed state space but is too small to significantly reduce the number timed states. Zones extend regions by representing larger equivalence classes using convex hulls [16]. These can be represented in di#erence bound matrices (DBMs) 16] since they represent allowed separations in a system, and many e#cient algorithms have been developed to manipulate DBMs [17] DBMs can also be implicitly represented [18, 19] A zone implicitly represents an allowed execution ....
....A region naturally address the continuous nature of the timed state space but is too small to significantly reduce the number timed states. Zones extend regions by representing larger equivalence classes using convex hulls [16] These can be represented in di#erence bound matrices (DBMs) [16] since they represent allowed separations in a system, and many e#cient algorithms have been developed to manipulate DBMs [17] DBMs can also be implicitly represented [18, 19] A zone implicitly represents an allowed execution trace in the circuit. A di#erent ordering on a set of concurrent ....
D. L. Dill. Timing assumptions and verification of finite-state concurrent systems. In Proc. of the Workshop on Automatic Verification Methods for Finite-State Systems, 1989.
Correctness and Reduction in Timed Circuit Analysis - Mercer (2002) (Correct)
....unique region generated at an untimed state during the trace evolution. A region naturally addresses the continuous nature of the timed state space but is too small to significantly reduce the number timed states. Zones extend regions by representing larger equivalence classes using convex hulls [63]. These can be represented in di#erence bound matrices (DBMs) since they represent allowed separations in a system [63] and many e#cient algorithms have been developed to manipulate DBMs. DBMs can also be implicitly represented [27] There have been several published algorithms using zones for ....
....of the timed state space but is too small to significantly reduce the number timed states. Zones extend regions by representing larger equivalence classes using convex hulls [63] These can be represented in di#erence bound matrices (DBMs) since they represent allowed separations in a system [63], and many e#cient algorithms have been developed to manipulate DBMs. DBMs can also be implicitly represented [27] There have been several published algorithms using zones for timing analysis. A tool for timed automata is presented in [23] A tool for time Petri nets is presented in [51] These ....
D. L. Dill, "Timing assumptions and verification of finite-state concurrent systems," in Proceedings of the Workshop on Automatic Verification Methods for Finite-State Systems, 1989.
Tools for Controller Synthesis of Timed Systems - Altisen, Tripakis (Correct)
....of quantifiers. In a first implementation, we used complementation to eliminate downloadable from www verimag.imag.fr TEMPORISE kronos 6 the alternations, but this is expensive, since complementations do not preserve convexity and cannot be implemented using the DBM data structure [13]. More e#cient ways to implement pre # have been developed in [1] and are currently used in SynthKro. They are based on a direct way of eliminating quantifiers, without complementation. Some examples of how this is done can be found in [24] We report performance results on three case ....
D.L. Dill. Timing assumptions and verification of finite-state concurrent systems. In J. Sifakis, editor, Automatic Verification Methods for Finite State Systems, Lecture Notes in Computer Science 407, pages 197--212. Springer-- Verlag, 1989. 11
On Timing Analysis of Combinational Circuits - Salah, Bozga, Maler (Correct)
....conservative low complexity approximations of the sub circuits to be used as inputs for the rest of the system. Some preliminary results of this methodology are reported. 1 Introduction It is well known that timed automata (TA) AD94] are well suited for modeling delays in digital circuits [D89,L89,MP95] Although some applications of TA technology for solving timing related problems for such circuits have been reported [MY96,BMPY97,TKB97,TKY 98,BMT99,BJMY02] the state and clock explosion associated with such models, restricted the applicability of TA to small circuits. In this ....
D. Dill, Timing Assumptions and Verification of Finite-State Concurrent Systems, in Automatic Verification Methods for Finite State Systems, LNCS 407, Springer, 1989.
Learning of Event-Recording Automata - Olga Grinchtein Bengt (Correct)
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D. Dill. Timing assumptions and verification of finite-state concurrent systems. In J. Sifakis, editor, Automatic Verification Methods for Finite-State Systems, LNCS
INFINITY 2004 Preliminary Version - Inference Of Timed (Correct)
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D. Dill. Timing assumptions and verification of finite-state concurrent systems. In J. Sifakis, editor, Automatic Verification Methods for Finite-State Systems, volume 407 of Lecture Notes in Computer Science. Springer Verlag, 1989.
Compositional Validation of Time-Critical Systems Using.. - Bucci, Vicario (1995) (17 citations) (Correct)
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D.Dill, "Timing Assumptions and Verification of Finite-State Concurrent Systems," Proc. of the Workshop on Computer Aided Verification Methods for Finite State Systems, Grenoble, France, 1989.
Timed Automata: Semantics, Algorithms and Tools - Bengtsson, Yi (Correct)
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David L. Dill. Timing assumptions and verification of finite-state concurrent systems. In Proceedings, Automatic Verification Methods for Finite State Systems, volume 407 of Lecture Notes in Computer Science, pages 197--212. Springer-Verlag, 1989.
Model Checking Timed Automata with One or Two Clocks - Laroussinie, Markey.. (2004) (Correct)
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D. L. Dill. Timing assumptions and verification of finite-state concurrent systems. In Proc. Int. Workshop Automatic Verification Methods for Finite State Systems (CAV'89), Grenoble, June 1989, volume 407 of Lecture Notes in Computer Science, pages 197--212. Springer, 1990.
Lower and Upper Bounds in Zone Based Abstractions of Timed.. - Behrmann, al. (2004) (1 citation) (Correct)
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David Dill. Timing assumptions and verification of finite-state concurrent systems. In Proc. of the Workshop on Automatic Verification Methods for Finite State Systems, volume 407 of Lecture Notes in Computer Science, pages 197--212. Springer, 1989.
Unknown - (Correct)
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D. Dill, Timing Assumptions and Verification of Finite-State Concurrent Systems, in J. Sifakis (Ed.), Automatic Verification Methods for Finite State Systems, LNCS 407, Springer, 1989.
Efficient Verification of Timed Automata using BDDs - Beyer, Noack (2001) (Correct)
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David L. Dill. Timing assumptions and verification of finite-state concurrent systems. In J. Sifakis, editor, Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems, LNCS 407, pages 197--212. Springer-Verlag, 1989.
Software Verification for Programmable Logic Controllers - Huuck (2003) (Correct)
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David Dill. Timing assumptions and verification of finite-state concurrent systems. In Joseph Sifakis, editor, International Workshop on Automatic Verification Methods for Finite State Systems, Grenoble, France, June 12--14, 1989, volume 407 of LNCS, pages 197--212. Springer-Verlag, 1990.
An Optimal Approach to Hardware/software Partitioning.. - Geguang, Yi, Van.. (2003) (1 citation) (Correct)
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D. Dill. Timing Assumptions and Verification of Finite-State Concurrent Systems. In Proc. of Automatic Verification Methods for Finite State Systems, LNCS 407, pp197-212, 1989.
Static Program Analysis via 3-Valued Logic - Thomas Reps Mooly (2004) (2 citations) (Correct)
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Dill, D.: Timing assumptions and verification of finite-state concurrent systems. In: Automatic Verification Methods for Finite State Systems. (1989) 197--212
Forward Analysis of Updatable Timed Automata - Bouyer (2004) (2 citations) (Correct)
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David Dill. Timing Assumptions and Verification of Finite-State Concurrent Systems. In Proc. of the Workshop on Automatic Verification Methods for Finite State Systems, vol. 407 of Lecture Notes in Computer Science, pp. 197--212. Springer, 1989.
Real-time System = Discrete System + Clock Variables - Alur, Henzinger (1997) (5 citations) (Correct)
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D.L. Dill. Timing assumptions and verification of finite-state concurrent systems. In J. Sifakis, editor, CAV 89: Automatic Verification Methods for Finite-state Systems, Lecture Notes in Computer Science 407, pages 197-- 212. Springer-Verlag, 1989. 48
Numeric Domains with Summarized Dimensions - Gopan, DiMaio, Dor, Reps, Sagiv (2004) (Correct)
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D.L. Dill. Timing assumptions and verification of finite-state concurrent systems. In Automatic Verification Methods for Finite State Systems, pages 197--212, 1989.
Alea jacta est - Verification of Probabilistic, Real-Time and.. - Stoelinga (2002) (Correct)
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D. Dill. Timing assumptions and verification of finite-state concurrent systems. In Hu and Vardi [HV98], pages 197--212.
Can Decision Diagrams Overcome State Space Explosion in.. - Beyer, Noack (2003) (Correct)
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David L. Dill. Timing assumptions and verification of finite-state concurrent systems. In Proc. Automatic Verification Methods for Finite State Systems, LNCS 407, pages 197--212. Springer, 1990.
Alea jacta est - Verification of Probabilistic, Real-Time and.. - Stoelinga (2002) (Correct)
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D. Dill. Timing assumptions and verification of finite-state concurrent systems. In Hu and Vardi [HV98], pages 197--212.
Verification of Asynchronous Circuits - Using Timed Automata (Correct)
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D.L. Dill, Timing Assumptions and Verification of Finite-State Concurrent Systems, in J. Sifakis (Ed.), Automatic Verification Methods for Finite State Systems, LNCS 407, 197-212, Springer, 1989.
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