L. Benini, A. Bogliolo and G. De Michelli, "A survey of design techniques for system-level dynamic power management", IEEE Transactions on VLSI Systems, vol. 8, no. 3, pp. 299-316, Jun. 2000. Home/Search Document Details and Download
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....system scheduling: dynamic voltage scaling (DVS) which varies the clock frequency and supply voltage according to the workload at run time; and dynamic power management (DPM) which aims to shut off system parts that are not currently in use. Excellent surveys on DVS and DPM can be found in [1] and [10] respectively. 3. Probabilistic Design Methodology Overview Many design methods have been developed based on WCET to meet the timing constraints without any deadline misses. These methods are pessimistic and are suitable for developing systems in a hard real time environment, where ....
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L. Benini, A. Bogliolo, and G. De Micheli. A survey of design techniques for system-level dynamic power management. IEEE Trans. on VLSI Systems, 8(3):299--316, 2000.
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L. Benini, A. Bogiolo, and G. De Micheli, "A survey of design techniques for system-level dynamic power management," IEEE Trans. VLSI Syst., vol. 8, pp. 299--316, June 2000.
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L. Benini, A. Bogliolo, and G. De Micheli,"A survey of design techniques for system-level dynamic power management," in IEEE Trans. on VLSI Systems, vol. 8, iss. 3, pp. 299--316, June 2000.
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L. Benini, A. Bogliolo, and G. D. Micheli). A survey of design techniques for system-level dynamicpower management. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 8(3):299--316, June 2000.
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