M. Martonosi, D. W. Clark, and M. Mesarina. The SHRIMP Performance Monitor: Design and Applications. In Proceedings SIGMETRICS Symposium on Parallel and Distributed Tools, pages 61--69, Philadelphia, May 1996.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....locality. In addition, it provides an essential basis for performance tools to tune the execution of parallel programs. Over the last years, monitoring support has become increasingly available on research as well as on commercial machines. Surprisingly, few hardware performance monitors [19] [20] have been developed for NUMA scenarios. The SMiLE hardware monitor as part of the event driven hybrid monitoring approaches provides the user with detailed information about low level memory transactions. Based on the statistics offered 6 by its low level software, data locality can be explictly ....

M. Martonosi, D. W. Clark, and M. Mesarina. The SHRIMP performance monitor: Design and applications. In Proc. SIGMETRICS Symposium on Parallel and Distributed Tools, pages 61--69, Philadelphia, May 1996.

....program the hardware for event triggering and actions processing on freely definable SCI regions. This addition to the monitor design was chosen to allow the user to include preknown memory areas that are supposed to be monitored regardlessly, much like in conventional histogram monitors [15]. Figure 3 shows a simplified view of the hardware structure used to realize this feature. All incoming transactions are handled through an eventfilter which comprises a page table and an event station. In combination both implement the ability to monitor memory regions and particular ....

....of research projects targets the increasingly important cluster architecture. Manzke et al. 14] present a monitoring hardware also for SCI which allows deep traces of SCI traffic, however, without the option of online address range selection and histograms like the SMiLE monitor. Martonosi et.al. [15] propose a monitoring approach for the SHRIMP multiprocessor based on Myrinet [3] However, this approach is implemented in software only as an additional Myrinet Control Program (MCP) run by the LANai processor and not directly in hardware [12] DSM Systems Work on shared memory models for ....

M. Martonosi, D. W. Clark, and M. Mesarina. The SHRIMP Performance Monitor: Design and Applications. In Proceeding 1996 SIGMETRICS Symnposium on Parallel and Distributed Tools (SPDT'96), pages 61--69, Philadelphia, PA, USA, May 1996. ACM.

....must be defined which adds the description of the new service requests of the tools into OMIS OCM system. 5 Related Work and Conclusion Over the last years, monitoring support has become increasingly available on research as well on commercial machines. The SHRIMP hardware performance monitor [9] has been developed to measure a running system s behavior. These measurement can be used to modify mutable parts of the system hardware, to help with software development and tuning, to characterize and evaluate the behavior and performance of a prototype system. Trinity College Dublin has ....

M. Martonosi, D. W. Clark, and M. Mesarina. The SHRIMP performance monitor: Design and applications. In Proc. SIGMETRICS Symposium on Parallel and Distributed Tools, pages 61--69, Philadelphia, May 1996.

....reference characteristics and hardware resource utilization. The monitor hardware can trace and count network events. This trace information can be used by high level protocols for a detailed analysis of the memory access patterns and overall application behaviors. The SHRIMP hardware monitor [13] can be used to keep watch on all packets arriving at a specific node. In contrast to our hybrid hardware monitor, it has a DRAM in the moni 6 tor card to record the complete access histograms and run time measurements of a running application. Similar to the SMiLE approach these measurements can ....

M. Martonosi, D. W. Clark, and M. Mesarina. The SHRIMP performance monitor: Design and applications. In Proc. SIGMETRICS Symposium on Parallel and Distributed Tools, pages 61--69, Philadelphia, May 1996.

....these unknown influential factors. There are many aspects of performance loss that are invisible to the programmer of parallel applications. Software tools can provide estimates of some of the sources of loss, but hardware is in general better suited to the task. For instance, tools such as CProf [21] 17 and MemSpy [8] can effectively do memory tuning to gain performance, but their simulation based property make them slow and cumbersome. Hardware is likely to be faster, more efficient and more accurate. In addition, these software tools cannot model contention well and they make assumptions ....

....and a hardware viewpoint. Monitoring in the NUMAchine memory is no more challenging than the hardware monitoring in the NUMAchine processor card [1] except that it meets the specifications that are required to be achieved. The Monitoring Unit implementation shares the use of a high capacity Altera [21] Flex 10K30 FPGA with the Special Functions Unit, another memory card component. This chapter is organised as follows. The NUMAchine memory subsystem and hierarchy are introduced, followed by an overview of the memory card. From there, the Monitoring Unit is described in detail. The monitor is ....

M. Martonosi, D.W. Clark, M. Mesarina, "The SHRIMP Performance Monitor: Design and Applications," First SIGMETRICS Symposium on Parallel and Distributed Tools, May 1996.

....support has become increasingly available on research as well as on commercial machines. The SHRIMP hardware performance monitor has been developed to measure the running behavior of the SHRIMP PC cluster, which is connected with special network adapters capable of performing remote updates [12]. In contrast to our hybrid hardware monitor, it has a DRAM in the monitor card to record the complete access histograms and run time measurements of running applications. Similar to the SMiLE approach, these measurement can be used to modify mutable parts of the system hardware and to help with ....

M. Martonosi, D. W. Clark, and M. Mesarina. The SHRIMP performance monitor: Design and applications. In Proc. SIGMETRICS Symposium on Parallel and Distributed Tools, pages 61--69, Philadelphia, May 1996.

....to explicitly program the hardware for event triggering and actions processing on SCI regions. This addition to the monitor design was chosen in order to allow the user to include preknown memory areas that are supposed to be monitored regardlessly, much like in conventional histogram monitors [13]. Figure 4 shows a simplified view of the hardware structure used to realize that features. The event filter comprises a page table and the event station. In combination both implement the ability to monitor memory regions and particular transactions upon them. The event stations specify the ....

....counters which collect information about data accesses, cache misses, TLB misses etc. For some multiprocessor systems these information is exploited by performance analysis tools [17] Martonosi et.al. propose a multi dimensional histogram performance monitor for the SHRIMP multiprocessor [13]. However, SHRIMP s new monitoring approach is based on Myrinet and implemented as additional Myrinet Control Program (MCP) run by the LANai processor [11] 6. Conclusion The paper describes the architecture and the inplementational details of the monitoring approach for the SMiLE SCI based PC ....

M. Martonosi, D. W. Clark, and M. Mesarina. The SHRIMP Performance Monitor: Design and Applications. In Proceeding 1996 SIGMETRICS Symnposium on Parallel and Distributed Tools (SPDT'96), pages 61--69, Philadelphia, PA, USA, May 1996. ACM.

....heavy performance monitoring, yet avoiding most of the undesirable probe effect of software instrumentation. Only a few DSM monitoring projects so far focused on providing hardware support for hardware based distributed shared memory. The performance monitor for the Princeton SHRIMP multicomputer [12] is one example can be configured to run as a trace monitor, using a high amount of local memory to store local traces without probe effect, or as a multidimensional histogram monitor. For the CCNUMA FLASH multiprocessor system [13] the hardwareimplemented cache coherence mechansism is ....

Margaret Martonosi, Douglas W. Clark, and Malena Mesarina, "The SHRIMP Performance Monitor: Design and Applications, " in Proceeding 1996 SIGMETRICS Symnposium on Parallel and Distributed Tools (SPDT'96), Philadelphia, PA, USA, May 1996, ACM, pp. 61--69.

.... In addition to application tuning, counters have many other uses, including predicting application performance and scalability for future processors and memory systems, analyzing architectural tradeoffs, generating address traces or address statistics, analyzing bus or communication traffic [15,17,23], evaluating compiler transformations, profiling the kernel [24] testing hardware, and characterizing workloads [7,8,27] Similar types of hardware counters have appeared in other processors. Counters have been used extensively on Cray vector processors [2] and appear, in some form, in ....

Margaret Martonosi, Douglas W. Clark and Malena Mesarina. The SHRIMP Performance Monitor: Design and Applications. ACM SIGMETRICS Symposium on Parallel and Distributed Tools, May 1996.

....1 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 89.55 89.552 89.554 89.556 89.558 89.56 Received Time (milliseconds) Received Time vs. Latency Figure 167: SIMPLE, No Combining, Run 1 45 5 Hardware Retrospective This section describes the di#erences between this design and the previously proposed design [16] as well as some lessons learned. 5.1 Design Di#erences Here is a list of some of the major design di#erences from the original performance monitor and the SurfBoard: Histogram address selection. Originally designed using an elaborate multiplexing scheme to allow immediate reconfiguration ....

....the SurfBoard) design, build, and test both components in parallel. Overlapping functionality (i.e. word count, histogram, and trace modes) simplified hardware debugging. 6 Related Work The design of the SurfBoard was originally based on the Shrimp performance monitor design described in [16]. This section discusses the relationship of the SurfBoard to several previously developed projects. For example, the Stanford DASH multiprocessor [15] included a per cluster histogram based performance monitor 46 [12] In the DASH monitor, histogramming is fixed at the time the FPGA was ....

M. Martonosi, D. Clark, and M. Mesarina. The SHRIMP Performance Monitor: Design and Applications. In ACM SIGMETRICS Symposium on Parallel and Distributed Tools, 1996.

....a wider variety of programs than FLASH. For this reason, a low level performance monitor that can be used for both shared memory and message passing programs is essential. This performance monitoring tool also derives some ideas from our previous hardware based performance monitor on Shrimp II [19]. They both implement the functionality of keeping packet based length and latency data in multipledimensional histograms. However, the hardware based monitor is a separate board from the network interface. It does not consume the processing power of the network interface, so it has an even ....

....we also expect that porting to similar systems with other programmable interface processors would be fairly straightforward. To gather low level statistics, our approach represents a significant improvement over previous reliance on simulation techniques or custom designed hardware monitor boards [12, 16, 19]. Acknowledgments This work was supported via DARPA contract N000014 951 1144, NSF grant MIP 9420653, and Intel Corporation. In addition, Margaret Martonosi is supported in part by an NSF Career Award CCR 95 02516. We thank the referees for their helpful suggestions. ....

M. Martonosi, D. W. Clark, and M. Mesarina. The SHRIMP Performance Monitor: Design and Applications. In ACM Sigmetrics Symposium on Parallel and Distributed Tools, May 1996.

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M. Martonosi, D. W. Clark, and M. Mesarina. The SHRIMP Performance Monitor: Design and Applications. In Proceedings SIGMETRICS Symposium on Parallel and Distributed Tools, pages 61--69, Philadelphia, May 1996.

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