P. Ivey, S. Walker, J. Stern, and S. Davidson. An ultra-high speed public key encryption processor. In Proceedings of IEEE Custom Integrated Circuits Conference, Boston, pages 19.6.119.6.4, 1992.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....existing public key systems. RSA encryption and signature veri cation can be speeded up signi cantly by selecting a small exponent b [32] Typical values used in practice are b = 3 and b = 2 1. The fastest existing hardware implementation of RSA can encrypt data at the rate of 64 Kbits sec [26] with a 512 bit modulus n. Software implementations on the Motorola DSP56000 which can encrypt at the rate of 13.4 Kbits sec [6] and 11.6 Kbits sec [18] have been reported for a 512 bit modulus. Integer Factorization Problem As mentioned before, the RSA cryptosystem is based on the integer ....

P. Ivey, S. Walker, J. Stern, and S. Davidson. An ultra-high speed public key encryption processor. In Proceedings of IEEE Custom Integrated Circuits Conference, Boston, pages 19.6.119.6.4, 1992.

....the modular squaring and multiply operations concurrently using two explicit modular multiplication units, or a single pipelined unit with the operations interleaved. The modular multiplication operation is performed using either conventional concurrent multiply and divide type algorithms ( 1] [59], 95] 113] 119] 121] and [128] or Montgomery s method ( 40] 57] 77] 94] 110] 131] 138] and [139] An alternative approach utilizes systolic arrays for modular multiplication exponentiation ( 28] 53] 61] 114] 127] and [130] though they are not typically used due ....

.... However, for those that have been reported, the DSRCP performs much better in terms of the time required to perform Design Power Consumption (W) Operand Size (bits) Time per Operation (ms) Cycles per Operation (Mcycles) Clock Rate (MHz) Ishii [57] 2W 1024 512 100 25 40 Ivey [59] 512 8 150 Orup [95] 512 5 0.125 25 Chen [28] 512 21 1.05 50 Yang [138] 512 4.3 0.54 125 Guo [53] 512 1.8 143 Leu [77] 512 4.6 0.53 115 Royo [110] 768 10.6 50 Satoh [113] 0.33 1024 23 45 Vandemeulebroecke [128] 0.5 1024 125 25 Shand [121] 1024 512 6 0.85 40 ....

P.A. Ivey, S.N. Walker, J.M. Stern, and S. Davidson, "An ultra-high speed public key encryption processor," Proceedings of the IEEE 1992 Custom Integrated Circuits Conference (CICC'92), 1992, pp. 19.6.1-19.6.4. 207

.... cryptosystem so a smaller memory can be used ffl ECC hardware implementations use less transistors, as an example, a VLSI implementation of 155 bit ECC has been reported which uses only 11,000 transistors [3] compared with an equivalent strength 512 bit RSA processor which used 50,000 transistors [4] ffl ECC is probably more secure than RSA, the largest RSA and ECC challenges solved being 512 bit and 97 bit respectively. In cracking the 97 bit ECC problem, approximately twice the computing power of the RSA problem was used. Previous implementations of ECC processors have been based on VLSI ....

J. S. P. Ivey, S. Walker and S. Davidson, "An ultra--high speed public key encryption processor, " in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 19.6.1--19.6.4, 1992.

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P. A. Ivey, S. N. Walker, J. M. Stern, and S. Davidson, "An ultrahighspeed public-key encryption processor," in Proc. IEEE 1992 Custom Integrated Circuits Conference (CICC'92), pp. 19.6.1--19.6.4.

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