Alur R. [1991], Techniques for Automatic Veri cation of Real{Time Systems, PhD thesis, Stanford University.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....that we do not want to distinguish between one delay step of duration, say, 1 and two subsequent delay steps of durations 2=5 and 3=5, since these traces are considered to be observationally equivalent. Logics without an explicit next step operator have also been considered, for example, by Alur [Alu91] by Henzinger, Nicollin, Sifakis, and Yovine [HNSY94] and by Dams [Dam96] Given a program M 2 Prg(C) and a path in M , the satis ability relation M; j= for an LTL(C) formula is given in the usual way with the notable exception of the case of constraint formulas c. In this case, M; j= ....

R. Alur. Techniques for Automatic Veri cation of Real-Time Systems. PhD thesis, Stanford University, 1991.

....to do this e ciently, and it remains an open problem to nd algorithms and data structures that work just as well for timed systems as bdds do for non timed systems. In general, the reachability problem for timed guarded commands is undecidable (i.e. the xpoint computation might not terminate) [1,11]. It is straightforward to model a register machine as a tgc program using a variable for each unbounded register, and a variable for the program counter. Test, increment, and decrement are easily expressed in assignments. An interesting task would be to identify conditions on tgc programs for ....

R. Alur. Techniques for Automatic Verication of Real-Time Systems. PhD thesis, Department of Computer Science, Stanford University, 1991.

.... In the untimed case, model checking algorithms with a polynomial time complexity, and often small space requirements, have been developed for several branching time temporal logics [12,14,25,29] In the timed case, most of the model checking problems considered in literature are PSPACE hard [5,6,31,42]. Clearly the quantitative analysis of timing constraints increases the complexity of model checking, but it is interesting to analyze precisely in which cases this complexity blow up occurs. In the untimed case, several papers (see, e.g. 32,37,67] study in detail the e ect of the temporal ....

....constants represented in unary or binary does not change our results except when it is explicitly mentioned. 3. 1 Reachability in Timed Automata Before embarking in our analysis of the complexity of model checking for L and its sublanguages, we recall a well known, and important, result [5,31] on the complexity of reachability in timed automata. The proof of such a statement is based upon an encoding of the workings of a Linear Bounded Turing Machine on a given input string by means of a timed automaton which will be used repeatedly in the technical developments to follow. Lemma 7 ....

R. Alur, Techniques for Automatic Verication of Real-time Systems, PhD thesis, Stanford University, 1991.

.... Automata [ACD93] There now exists a large body of theoretical knowledge and practical experience for this class of systems, and it is agreed that their main drawback is the complexity blowup induced by timing constraints: all model checking problems are at least PSPACE hard over Timed Automata [Alu91,CY92,ACD93,AL99]. However, there exist simpler families of timed models, for which polynomialtime model checking is possible. Usually, these are based on classical, discrete, Kripke structures (KS) Here there is no inherent concept of time (contrary to clocks in Timed Automata) and the elapsing of time is ....

R. Alur. Techniques for Automatic Verication of Real-Time Systems. PhD thesis, Stanford Univ., August 1991. Available as Tech. Report STAN-CS91 -1378.

....classes, otherwise, the state space is in nite. All timing behaviors within an equivalence class must lead to the same state and do not need to be explored separately. Therefore, the size of equivalences should be as large as possible to reduce the number of timed states. In the region approach [1], timed states with the same integral clock values and a particular linear ordering of the fractional values of the clocks are equivalent. Although this approach eliminates the need to discretize time, the state space can explode if the delay ranges are large. Another approach to continuous time ....

....traces after Reduction 1 is applied to them. The abstracted TEL for the one shown in Figure 5.10(a) is shown in Figure 5.10(c) Another example is shown 80 a b c or c a c b a b c (a) b) c) Figure 5.10. An example of a sequencing event with a con ict in its preset. a b c d [1,5] [1,3] 4,7] 2,6] a b d a b c or [1,5] 2,6] 1,5] 2,6] 1.3] 4,7] c d # a b [2,8] 6,13] 3,9] 5,12] a) b) c) Figure 5.11. An example of a sequencing event where its postset has multiple rules but only one con ict place. in Figure 5.11(a) where there are two rules in ....

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Alur, R. Techniques for Automatic Verication of Real-Time Systems. PhD thesis, Stanford University, August 1991.

....analog the proof of Theorem 1. 2 In [Sor01] it is shown that the model checking problem for xpoint eventrecording logic ERL is decidable. Thus, timed bisimulation and timed simulation are decidable. Since the reachability problem for timed automata is PSPACE hard, as shown by Alur in [Alu91], the model checking problem for event recording automata and ERL is PSPACE hard. Corollary 1 The model checking problem for ERL is PSPACE hard. As a consequence of Theorems 2 and 1 and Corollary 1 the following holds. Corollary 2 The problem of deciding whether two event recording automata ....

R. Alur. Techniques for Automatic Verication of Real-Time Systems. PhD thesis, Stanford University, 1991.

....in [37, 38] and recently, an implicit approach in [39] discretely model time in the state space. Unfortunately, this state space explodes if the delay ranges are suciently large and the discrete time constant suciently small to nd an exact state space. Continuous time methods using regions in [17, 16, 40] more naturally address the continuous nature of the timed state space. Zones in [41] extend regions by representing larger equivalence classes with convex hulls. Although the worst case complexity of zones is larger than that of regions, the zone method often results in a smaller state space ....

....cation of timed circuits is found in [44, 45, 46, 47] Partial order state space exploration and zones are combined in [20] yielding a signi cant reduction in the explored timed state space. The method in [20] still retains a worst case complexity that is greater than the simpler region method of [16, 17, 40], but due to the partial exploration of the state space, this complexity has less impact on the total veri cation problem. 3 3 Essential ATACS ATACS is a CAD tool for the synthesis and veri cation of timed circuits [3] ATACS takes speci cations and compiles them into Timed event level (TEL) ....

R. Alur. Techniques for Automatic Verication of Real-Time Systems. PhD thesis, Stanford University, August 1991.

....time delays while preserving all properties of interest. We show how the time abstracting quotient graph of a GTA can be viewed as a game graph so that GTA controller synthesis is reduced to GG controller synthesis. We illustrate our approach on a toy example, the Train Gate Controller system of [Alu91] viewed as a GTA) We show how a strategy can be obtained for this system in an on the y manner, that is, without having to explore the whole quotient graph. Relation to the literature. Controller synthesis is close to the theory of games . In the domain of formal methods, pioneering have ....

Rajeev Alur. Techniques for Automatic Verication of Real-Time Systems. PhD thesis, Department of Computer Science, Stanford University, 1991.

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Alur R. [1991], Techniques for Automatic Veri cation of Real{Time Systems, PhD thesis, Stanford University.

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Alur, R., \Techniques for Automatic Verication of Real-Time Systems," Ph.D. thesis, Stanford University, 1991.

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