R. P. Dick, N. K. Jha, "MOCSYN: Multiobjectivecore-basedsingle-chip system synthesis, " Design Automation and Test in Europe Conf., pp.263-270, 1999. Home/Search Document Details and Download
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Functional Partitioning for Low Power Distributed Systems of.. - Fei, Jha Self-citation (Jha) (Correct)
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R. P. Dick and N. K. Jha, "MOCSYN: Multiobjective core-based single-chip system synthesis," in Proc. Design Automation & Test in Europe Conf., pp. 263-270, Mar. 1999.
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R. P. Dick and N. K. Jha, MOCSYN: Multiobjective corebased single-chip system synthesis," in Proc. Design, Automation and Test in Europe, pp. 263-270, Mar. 1999.
A High-level Interconnect Power Model for Design Space.. - Gupta, Zhong, Jha (2003) Self-citation (Jha) (Correct)
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R. P. Dick and N. K. Jha, "MOCSYN: Multiobjective core-based singlechip system synthesis," in Proc. Design Automation and Test in Europe Conf., Mar. 1999, pp. 263--270.
Multiobjective Synthesis of Low-Power Real-Time Distributed.. - Dick (2002) (1 citation) Self-citation (Dick) (Correct)
....and efficient bus topology generation algorithm that optimizes communication contention under routability constraints. We proposed a new system on chip clock selection method. Our experiments demonstrate that it is important to consider a number of low level details during system on chip synthesis [204]. We were the first to synthesize heterogeneous distributed systems containing dynamically reconfigurable hardware [205] although others had started work on this problem at our time of publication [69] Our scheduler considers, and minimizes, inter task reconfiguration delay. We demonstrate that ....
R. P. Dick and N. K. Jha, "MOCSYN: Multiobjective core-based single-chip system synthesis," in Proc. of Design, Automation and Test in Europe Conf., pp. 263-- 270, Mar. 1999.
Battery-aware Static Scheduling for Distributed Real-time.. - Luo, Jha (2001) (27 citations) Self-citation (Jha) (Correct)
....scheme can lead to better results, as the difference between Fig. 6(b) and Fig. 7(b) shows. 4. Static Resource Allocation, Assignment and Scheduling The static resource allocation, task communication assignment and scheduling algorithms we use are from a system synthesis t ool presented in [12]. It uses a slack based list scheduling algorithm to generate static PE and communication link schedules for each task and communication event along the hyperperiod, which is the least common multiple of all the task graph periods in a multi rate system specification. It is well known that there ....
R. P. Dick and N. K. Jha, "MOCSYN: Multiobjective corebased single-chip system synthesis," in Proc. Design Automation & Test in Europe Conf., pp. 263-270, Mar. 1999.
Power-conscious Joint Scheduling of Periodic Task Graphs and.. - Luo, Jha (2000) (24 citations) Self-citation (Jha) (Correct)
....2.55 Power 1 1 1 0.87 Table 3: Aperiodic Task Response Time and Power Consumption for the Different Schemes 3. Static Resource Allocation, Assignment and Scheduling The static resource allocation, task communication assignment and scheduling algorithm we use is from a system synthesis tool [18]. It uses a slack based list scheduling algorithm to generate static PE and communication link schedules for each task and communication event along the hyperperiod, which is the least common multiple of all the task graph periods in a multi rate system specification. It is well known that there ....
....is well known that there exists a feasible schedule for the periodic task graphs if and only if there exists a feasible schedule for the hyperperiod [19] Static scheduling makes it possible to guarantee that hard real time constraints of periodic task graphs will be met. The static schedule from [18] is modified with a post processing stage, as explained later in Section 7. 4. Handling of Hard Aperiodic Tasks One approach to handle hard aperiodic tasks is to reserve execution slots for them at regular intervals throughout the hyperperiod [7] The hard aperiodic tasks are always executed at ....
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R. P. Dick and N. K. Jha, "MOCSYN: Multiobjective corebased single-chip system synthesis," in Proc. Design Automation & Test in Europe Conf., pp. 263-270, Mar. 1999.
Layout Conscious Bus Architecture Synthesis for Deep.. - Thepayasuwan, Doboli (2003) (1 citation) (Correct)
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R. P. Dick, N. K. Jha, "MOCSYN: Multiobjectivecore-basedsingle-chip system synthesis, " Design Automation and Test in Europe Conf., pp.263-270, 1999.
Bus Architecture Synthesis for Hardware-Software.. - Thepayasuwan, Damle.. (2003) (Correct)
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R. P. Dick, N. K. Jha, "MOCSYN: Multiobjective core-based single-chip system synthesis," Design Automation and Test in Europe Conf., pp.263-270, 1999.
Power-Aware Resource Allocation for Independent Tasks in.. - Yu, Prasanna (Correct)
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R. P. Dick and N. K. Jha. MOCSYN: Multiobjective core-based single-chip system synthesis. In Design Automation & Test in Europe Conference, pages 263-270, Mar. 1999.
Methods for Evaluating and Covering the Design Space during Early.. - Gries (2004) (2 citations) (Correct)
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R. P. Dick, N. K. Jha, MOCSYN: Multiobjective core-based single-chip system synthesis, in: Design, Automation and Test in Europe Conference (DATE), 1999, pp. 263--270.
Resource Allocation for Independent Real-Time Tasks in.. - Yu, Prasanna (Correct)
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R. P. Dick and N. K. Jha. MOCSYN: Multiobjective core-based single-chip system synthesis. In Design Automation & Test in Europe Conference, pages 263-270, Mar. 1999.
Methods for Evaluating and Covering the Design Space during Early.. - Gries (2003) (2 citations) (Correct)
No context found.
R. P. Dick and N. K. Jha. MOCSYN: Multiobjective core-based single-chip system synthesis. In Design, Automation and Test in Europe Conference (DATE), pages 263--270, 1999.
Fast and Efficient Voltage Scheduling by Evolutionary Slack .. - Bita Gorji-Ara Pai (Correct)
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R.P. Dick and N.K. Jha, "MOCSYN: multi-objective corebased single-chip system synthesis". In Proc. DATE , pp. 263270, Mar. 1999.
Static Priority Scheduling of Event-Triggered.. - Erbas, Cerav-Erbas.. (2004) (Correct)
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R. P. Dick and N. K. Jha. MOCSYN: Multiobjective corebased single-chip system synthesis. In Proc. of the Design, Automation and Test in Europe, Mar. 1999.
Memory Aware Task Assignment and Scheduling for Multiprocessor.. - Szymanek (2001) (1 citation) (Correct)
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Dick, R.P.; Jha, N.K., "MOCSYN: multiobjective corebased single-chip system synthesis", in Proc. Design, Automation and Test in Europe Conference, 1999, Page(s): 263-270.
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