J. Engblom and A. Ermedahl. Pipeline Timing Analysis Using a Trace-Driven Simulator. In Proc. 6 Systems and Applications (RTCSA'99). IEEE Computer Society Press, Dec 1999.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....and can handle complex flow constraints very well, but may be costly. The basic IPET model assumes that the total execution time is independent of execution order. This holds only for simple CPU architectures. IPET has however been generalized to handle architectural features like pipelines [11] and caches [25] For simplicity, we will only consider the basic IPET model here, but our method applies to the same problems as general IPET. Parametric WCET analysis methods return a parameterized expression. These may be unknown parameters to the program, or represent unknown program flow ....

....assign it to p in F (abstract starting state) solve the equations over F . The number of elements in S bounds the number of times the path P can be taken, given that we start from some state in S . This information can be used directly in IPET calculations with pipeline timing effects [11]. The sum of the execution counts of two basic blocks in a loop can also be bound (infeasible path analysis) If p and q are in a loop with upper bound N for the iteration count, then the flow constraint x p x q N jS j is valid. i = k i = k 1 p no no yes yes Figure 4: Loop body ....

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J. Engblom and A. Ermedahl. Pipeline Timing Analysis Using a Trace-Driven Simulator. In Proc. 6 International Conference on Real-Time Computing Systems and Applications (RTCSA'99). IEEE Computer Society Press, Dec. 1999.

....features, as for instance F. Mueller s static cache simula tion [14] which statically simulates all possible contents of the cache by considering possible execution paths all at once. Several works use static simulation techniques to take into account architectural features such as pipelines [5, 8, 21], instruction caches [14, 11, 8, 21] cache hierarchies [14] data caches [9] and branch prediction [3] Most timing analysis approaches that integrate several of the above static simulation techniques (usually cache and pipeline) into a single static WCET analysis method lead to static WCET ....

J. Engblom and A. Ermedahl. Pipeline timing analysis using a trace-driven simulator. In Proc. of the 6th International Conference on Real-Time Computing Systems and Applications (RTCSA '99). IEEE Computer Society Press, December 1999.

....features, as for instance F. Mueller s static cache simulation [13] which statically simulates all possible contents of the cache by considering possible execution paths all at once. Several works use static simulation techniques to take into account architectural features such as pipelines [5, 8, 20], instruction caches [13, 11, 8, 20] cache hierarchies [13] data caches [9] and branch prediction [2] Most timing analysis approaches that integrate several of the above static simulation techniques (usually cache and pipeline) into a single static WCET analysis method lead to static WCET ....

J. Engblom and A. Ermedahl. Pipeline timing analysis using a trace-driven simulator. In Proc. of the 6th International Conference on Real-Time Computing Systems and Applications (RTCSA'99). 1EEE Computer Society Press, Dec. 1999.

....of an instruction on modern processors can depend on the execution context, that is, on the neighboring instructions. In the presence of pipeline and cache memories, it may only be reasonable to measure the execution time of instruction sequences. Such an approach is used by Engblom and Ermedahl [2]. To account for pipeline timing effects, Engblom and Ermedahl present an algorithm that first assesses the execution time of one sequence of instructions, then of two sequences, r#p#, until all timing effects have been captured. However, the timing of the sequences is assessed by a simulator, not ....

Engblom, J., and Ermedahl, A. "Pipeline Timing Analysis Using a Trace-Driven Simulator". In Q...'p#'s #ur%#uD###SR 'sr...rpr'Srhy#Uvr8'f#vtT'+# #r+hq6ffyvph#v'+#SU8T6##2R , Hong Kong, December 13-15, 1999. IEEE Computer Society Press.

....Finding WCET of programs using dynamic testing methods has been studied by several research groups. Approaches using Genetic algorithms seem to be the most successful ones, see e.g. 17] However, no guarantee can be given regarding the safeness of the results. Static analysis methods, e.g. [6, 11], use either cyclelevel simulators or other models of the hardware to compute the execution time of individual basic blocks. Since, our work is based on the assumption that accurate hardware models are non existing or difficult to construct these approaches are not sufficient for us. However, if ....

J. Engblom and A. Ermedahl. Pipeline Timing Analysis Using a Trace-Driven Simulator. In Proc. International Conference on Real-Time Computing Systems and Applications, 1999.

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J. Engblom and A. Ermedahl. Pipeline Timing Analysis Using a Trace-Driven Simulator. In Proc. 6 Systems and Applications (RTCSA'99). IEEE Computer Society Press, Dec 1999.

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J. Engblom and A. Ermedahl. Pipeline timing analysis using a trace-driven simulator. In Proc. 6 International Conference on Real-Time Computing Systems and Applications (RTCSA'99). IEEE Computer Society Press, December 1999.

....real time systems complicates static WCET analysis (and the measuring of execution times) by increasing the variability in execution time and by requiring more complex analysis methods. A variety of concrete analysis methods for pipelines have been proposed, ranging over cycle accurate simulators [6, 7, 22], special purpose models using reservation tables [4, 9, 14, 21] dependence graphs [15] abstract interpretation of pipeline behavior [8, 20] and tables of instruction execution times and inter instruction effects [2, 3] The timing benefit (effect) of pipelines is to a large extent due to the ....

....For many pipelines, there are also timing effects that only occur for sequences of three or more instructions; in this case the entire sequence has to be considered in a precise and safe timing analysis that involves the first instruction. Such long timing effects (LTEs) are introduced in [7]. In this paper, we investigate general properties of pipelines relevant for static WCET analysis, in particular the issue of how far away a single instruction in a program can affect the pipeline behavior of other instructions. Sometimes, it is enough to consider pairs of adjacent instructions, ....

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J. Engblom and A. Ermedahl. Pipeline Timing Analysis Using a Trace-Driven Simulator. International Conference on Real-Time Computing Systems and Applications (RTCSA'99). IEEE Computer Society Press, December 1999.

....further divided into two stages. Global low level analysis takes features requiring a global view (caches, branch predictors) into account [5, 14, 16, 18, 20, 21, 24, 25, 33, 36] Local low level analysis considers features with local effects, like pipelines and superscalar instruction execution [9, 10, 16, 21, 22, 32, 33]. Three classes of calculation methods are mainly used: tree based calculation, pathbased calculation, and the Implicit Path Enumeration Technique (IPET) The tree based approach is limited to well structured codes, and assumes that the execution time bounds for programs can be directly derived ....

....architecture of the tool makes it possible to simply plug in low level analyses of new processors as the need arises. We have also implemented an instruction cache analysis similar to the one described by Ferdinand et al. 14] but we have not used this analysis in the current experiments. See [9, 10] for details. Information about possible program flows is communicated to the low level analysis and WCET calculation through flow facts, a certain constraint format [11] Flow facts are constraints on execution counters that give the number of times certain edges or nodes in the control flow ....

J. Engblom and A. Ermedahl. Pipeline Timing Analysis Using a Trace-Driven Simulator. In Proc. 6 International Conference on Real-Time Computing Systems and Applications (RTCSA'99). IEEE Computer Society Press, Dec. 1999.

....the execution time for each atomic unit of ow (e.g. an instruction or a basic block) given the architecture and features of the target system. For WCET analysis, instruction caches [10, 11, 15, 25] cache hierarchies [19] data caches [13, 25, 27] branch predictors [3] scalar pipelines [7, 11, 15] and superscalar CPUs [16, 24, 25] have been analysed. The purpose of the calculation phase is to calculate the WCET estimate for a program, given the program ow and global and local low level analysis results. There are three main categories of calculation methods proposed in literature: path ....

....with a count variable also has a time variable (t entity ) giving the contribution of that part of the program to the total execution time for each time it is executed. As shown in our previous work, the modeling method can handle both individual execution scenario nodes and sequences of nodes [7]. The ow possible given the structure of the program is modeled using structural constraints. For each node, the sum of the incoming ows is equal to the outgoing ows. For example, for node B in Figure 3 the constraints x AB x EB = x B and x B = x BC x BD would be generated. The structural ....

[Article contains additional citation context not shown here]

J. Engblom and A. Ermedahl. Pipeline timing analysis using a trace-driven simulator. In Proc. 6 th International Conference on Real-Time Computing Systems and Applications (RTCSA'99). IEEE Computer Society Press, December 1999.

....handled locally for an instruction and its neighbors. In global low level analysis, instruction caches [11, 14, 18, 29] cache hierarchies [22] data caches [16, 29, 31] and branch predictors [4] have been analyzed. Local low level analysis has built software models to deal with scalar pipelines [7, 14, 18] and superscalar CPUs [19, 28, 29] For some complex architectures attempts have been made to use the hardware itself [25] 2 Local Low Level Analysis Calculation Global Low Level Analysis Compiler Flow Analysis WCET Program Source Input Data Timing Effect Expansion Scope Graph ....

....similar to the one described by Ferdinand et al. 11] but we do not use the analysis in the current experiments, since our target hardware does not have a cache. Figure 1 still shows that such an analysis would fit in, by modifying the scope graph to include cache information as described in [7, 9]. Cache and other global low level analysis results are used in the pipeline analysis as described in Section 3.2 below. 3 loop bound: 10 outer: 1. 5 :x I =1 loop bound: 20 inner: x C x F 1 inner: 6. 10 :x C =0 inner: 1. 8 :x C x G D E C B scope inner scope outer x A x D ....

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J. Engblom and A. Ermedahl. Pipeline timing analysis using a trace-driven simulator. In Proc. 6 th International Conference on Real-Time Computing Systems and Applications (RTCSA'99). IEEE Computer Society Press, December 1999.

....typically takes several extra cycles to access. Pessimistic (approximate but safe) approaches are common, e.g. assuming there is a pipeline speed up effect only when enough pipeline content information is available to guarantee the e#ect. Researchers have considered simple scalar pipelines [32, 40, 13, 23] and superscalar CPU pipelines [33, 47, 49] Calculation The purpose of the calculation is to calculate the WCET estimate for the program, given the program flow and global and local low level analysis results. There are three main categories of calculation methods proposed in literature: path , ....

....The process is illustrated in Figure 10. The timing e#ect for the edge QR is 22 15 11 = 4; the time is negative since the two nodes Q and R overlap. The details of these issues, and how to handle pipeline timing e#ects appearing over sequences of nodes longer than two, are given in [13]. Simulators are a standard part of embedded development environments today, and are often provided by the chip manufacturers. We expect to utilize this fact to quickly port our pipeline analysis to new chips. 7. Calculation The purpose of the Calculation phase is to calculate the final WCET ....

[Article contains additional citation context not shown here]

J. Engblom and A. Ermedahl. Pipeline Timing Analysis Using a Trace-Driven Simulator. In Proc. 6 th International Conference on Real-Time Computing Systems and Applications (RTCSA'99). IEEE Computer Society Press, December 1999.

....the error source. In this paper we present a testing methodology designed to isolate the potential errors in each component of a WCET analysis. We demonstrate the applicability of the methodology on the pipeline analysis and the calculation phase of our previously published WCET analysis method [1]. 2. WCET Phases and Related Work To generate a WCET estimate, we consider a program to be processed through the phases of program flow analysis, global low level analysis, local low level analysis and calculation. The program flow analysis phase determines the dynamic behaviour of the program. ....

....to our tool in order to test the correctness of the local low level (pipeline) analysis and the calculation method. 3.1. Architecture of our WCET Tool Figure 1 gives an overview of our WCET analysis system as implemented today. It is a concrete implementation based on the principles presented in [1]. Since the architecture is very modular, testing is simplified. Each component has clearly defined roles and interfaces, and to produce a correct tool, wewant to test the correctness of each component in isolation. We manually inspect the object code, source code, and input data of the test ....

[Article contains additional citation context not shown here]

J. Engblom and A. Ermedahl. Pipeline timing analysis using a trace-driven simulator. In Proc. 6 th International ConferenceonReal-Time Computing Systems and Applications (RTCSA'99). IEEE Computer Society Press, December 1999.

....the execution time for each atomic unit of flow (e.g. an instruction or a basic block) given the architecture and features of the target system. For WCET analysis, instruction caches [10, 11, 15, 25] cache hierarchies [19] data caches [13, 25, 27] branch predictors [3] scalar pipelines [7, 11, 15] and superscalar CPUs [16, 24, 25] have been analysed. The purpose of the calculation phase is to calculate the WCET estimate for a program, given the program flow and global and local low level analysis results. There are three main categories of calculation methods proposed in literature: path ....

....with a count variable also has a time variable (t entity ) giving the contribution of that part of the program to the total execution time for each time it is executed. As shown in our previous work, the modeling method can handle both individual execution scenario nodes and sequences of nodes [7]. The flow possible given the structure of the program is modeled using structural constraints. For each node, the sum of the incoming flows is equal to the outgoing flows. For example, for node B in Figure 3 the constraints x AB x EB = x B and x B = x BC x BD would be generated. The ....

[Article contains additional citation context not shown here]

J. Engblom and A. Ermedahl. Pipeline timing analysis using a trace-driven simulator. In Proc. 6 th International Conference on Real-Time Computing Systems and Applications (RTCSA'99). IEEE Computer Society Press, December 1999.

.... Gus00] and one based on structural analysis of loops [HSRW98, HSR 00] ffl A compact and efficient method for representing information about the control flow of a program [EE00a] ffl A pipeline analysis method that uses a generic CPU simulator instead of a special purpose WCET CPU model [EE99] ffl A calculation method that allows control flow and hardware analysis results (including the effects of caches) to be integrated and used to efficiently calculate tight and safe WCET estimates [OS97, EE99, EE00a] ffl A method for validating the components of our WCET tool, aiming at a ....

.... method that uses a generic CPU simulator instead of a special purpose WCET CPU model [EE99] ffl A calculation method that allows control flow and hardware analysis results (including the effects of caches) to be integrated and used to efficiently calculate tight and safe WCET estimates [OS97, EE99, EE00a] ffl A method for validating the components of our WCET tool, aiming at a complete validation of the entire tool suite [EE00b] ffl We have investigated the properties of commercial embedded real time programs and the attitudes of real time practitioners regarding WCET tools and WCET ....

[Article contains additional citation context not shown here]

J. Engblom and A. Ermedahl. Pipeline Timing Analysis Using a Trace-Driven Simulator. In Proc. 6 th International Conference on Real-Time Computing Systems and Applications (RTCSA'99). IEEE Computer Society Press, December 1999.

No context found.

J. Engblom and A. Ermedahl. Pipeline timing analysis using a trace-driven simulator. In Proc. 6th International Conference on Real-Time Computing Systems and Applications, Hong Kong, Dec. 1999.

No context found.

J. Engblom and A. Ermedahl. Pipeline Timing Analysis Using a Trace-Driven Simulator. In Sixth International Conferenco on Real-Time Computing Systems and Applications (RTCSA). IEEE, 1999.

No context found.

Jakob Engblom and Andreas Ermedahl. Pipeline timing analysis using a trace-driven simulator. In Proc. 6th International Conference on Real-Time Computing Systems and Applications, Hong Kong, Dec. 1999.

No context found.

Jakob Engblom and Andreas Ermedahl. Pipeline timing analysis using a trace-driven simulator. In Proc. 6th International Conference on Real-Time Computing Systems and Applications, Hong Kong, Dec. 1999.

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