N. Narasimhan, E. Teica, R. Radhakrishnan, S. Govindarajan, and R. Vemuri, "Theorem proving guided development of formal assertions in a resource-constrained scheduler for high-level synthesis, " in International Conference on Computer Design 1998. Home/Search Document Details and Download
Summary Related Articles Check |
This paper is cited in the following contexts:
Accounting for Various Register Allocation Schemes During.. - Mansouri, Vemuri (Correct)
....Research in formal verification of synthesized designs, can be classified as transformation based synthesis (formal synthesis) and post synthesis verification. In formal synthesis, the transformations which may be carried out during the synthesis process, are mathematically proven correct [1 7]. Unfortunately, even though it guarantees designs that are correct by construction, transformation synthesis is largely interactive. In postsynthesis verification the correctness of a synthesized design, with respect to its specification, is mathematically established [8 12] This approach is ....
N. Narasimhan et al, "Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis", ICCD'98, October 1998.
Automated Correctness Condition Generation for Formal.. - Mansouri, Vemuri (1999) Self-citation (Vemuri) (Correct)
....are automatically generated during the synthesis process. The approach presented in this paper has a similar goal, but aims to incorporate proof obligation generation within the context of conventional target architectures used by traditional high level synthesis tools. Narasimhan and Vemuri [33, 36] systematically formulated the correctness properties for certain high level synthesis stages. They identified a set of assertions and invariants that should hold at various steps of high level synthesis process. These invariants were inserted in the high level synthesis tool DSS [41] to detect ....
Narasimhan, N., E. Teica, R. Radhakrishnan, S. Govindarajan, and R. Vemuri: 1998, `Theorem Proving Guided Development of Formal Assertions in a R esource-Constrained Scheduler for High-Level Synthesis'. Proceedings of International Conference on Computer Design (ICCD'98) pp. 392--399.
Combined Temporal Partitioning and Scheduling for.. - Pandey, Vemuri Self-citation (Vemuri) (Correct)
....INPUTS OUTPUTS SHARED MEMORY (RAM) CONFIGURATION MEMORY(ROM) Local Local Local Local Memory Memory Memory Memory Figure 2. Typical RC Architecture segments, and store the results from the segments. For our experiments, we use one processing element with 576 CLBs. We use Asserta [6, 14] which is an in house behavioral synthesis tool. Commercial CAD tools such as Synplify Logic Synthesis tool, Xilinx Place and Route tools are used to generate the FPGA bitstreams for the Wildforce system. The processing element is configured from a software program that loads the input data in the ....
N. Narasimhan, E. Teica, R. Radhakrishnan, S. Govindarajan and R. Vemuri, "Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis". Proceedings of International Conference on Computer Design, ICCD'98. October 1998
On the Efficiency of Formal Synthesis - Experimental.. - Blumenrohr.. (1999) (Correct)
No context found.
N. Narasimhan, E. Teica, R. Radhakrishnan, S. Govindarajan, and R. Vemuri, "Theorem proving guided development of formal assertions in a resource-constrained scheduler for high-level synthesis, " in International Conference on Computer Design 1998.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC