K. Ware, et al., "A 200-MHz CMOS Phase-Locked Loop with Dual Phase Detectors, " IEEE J. Solid-State Circuits, vol. SC-24, no. 6, pp. 1560-1568, Dec. 1989. Home/Search Document Not in Database Summary Related Articles Check |
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Precise Delay Generation Using Coupled Oscillators - Maneatis (1994) (18 citations) (Correct)
....stage can be improved by using a current source with a higher output impedance. However, supply voltage limitations will impact the options available for accomplishing the current source isolation. The supply isolation can be accomplished by using cascode current [14] sources or supply filtering [15]. With supply filtering, an intermediate supply voltage is produced from a reference voltage that is independent of supply voltage. This approach is more conducive to buffer designs where delay control is achieved by adjusting the intermediate supply voltage. When inadequate supply voltage is ....
K. Ware, et al., "A 200-MHz CMOS Phase-Locked Loop with Dual Phase Detectors, " IEEE J. Solid-State Circuits, vol. SC-24, no. 6, pp. 1560-1568, Dec. 1989.
IV.9 Clock Input Buffer and Delay-Locked Loop - Ed Lo Op (Correct)
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K. Ware, Lee, H.-S., and Sodini, C., "A 200MHz CMOS Phase-Locked Loop with Dual Phase Detectors", ISSCC 89, pp 192-193.
Design of High-Speed, Low-Power Frequency Dividers and.. - Razavi, Lee, Yan (1995) (4 citations) (Correct)
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K. M. Ware, H. S. Lee, and C. G. Sodini, "A 200-MHz CMOS phaselocked loop with dual phase detectors," IEEE J. Solid-State Circuits, vol. 24, pp. 1560--1568, Dec. 1989. RAZAVI et al.: DESIGN OF HIGH-SPEED, LOW-POWER FREQUENCY DIVIDERS 109
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