Asgeir Th. Eirksson, John Keen, Alex Silbey, Swami Venkataraman, and Michael Woodacre. Origin system design methodology and experience: 1m-gate asics and beyond. In COMPCON-97, 1997.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....a given property to be correct because it was indirectly verified. For example, using emulation to construct a prototype of a multiprocessor and then executing benchmark programs to implicitly verify data coherence. References to prior work Correctness Property [14, 15] 16, 17] 18, 19] [20, 21] [22, 23] Data coherence I E E E Preservation of program order E E High level Properties Write serialization E E Wr i t e propaga t on I I I I Write atomicity E Absence of livelock deadlock I I I E E Implementation Specific Fairness Properties Single writer E E Unexpected message ....

....reflects the actual system and the assumptions made during the verification of the properties. Examples of architectural model checking Contemporary multiprocessors, such as the SGI Origin2000 [28] have encountered design challenges and addressed these obstacles with innovative methodologies [21] that include formal verification as well as traditional simulation. By integrating formal analysis and verification into the design process [20] critical design bugs were discovered with the coherence protocol that would have been difficult, if not impossible, to find using conventional logic ....

Asgeir Th. Eir iksson, John Keen, Alex Silbey, Swami Venkataraman, and Michael Woodacre. Origin system design methodology and experience: 1m-gate asics and beyond. In COMPCON-97, 1997.

....on a single processor, on a set of distributed processors, and on a shared memory multiprocessor. keywords: multiprocessor, distributed shared memory, verification, simulation, high level validation 1 Introduction Contemporary multiprocessors, such as the Cray T3E [2] and the SGI Origin [3, 4], have tens of millions of gates per node. This complexity makes the verification of the design a very problematic and time consuming endeavor. This verification problem is rooted in the exponential growth of IC technology. As design complexity and integration increase, the verification challenges ....

Asgeir Th. Eir iksson, John Keen, Alex Silbey, Swami Venkataraman, and Michael Woodacre, "Origin System Design Methodology and Experience: 1M-gate ASICs and Beyond," COMPCON-97.

....program execution. Obviously, it is impossible to conclude that, if the system is correct for a given program execution, it must be correct for all executions and all programs. More recently, formal verification methods have been used to validate the coherence protocol of the SGI Origin2000 [15, 16, 17] and the Sun S3.mp (Sun Scalable Shared Memory Multiprocessor) 18, 19] Eir iksson used the Symbolic Model Verifier (SMV) 20] to verify an abstract model of a three node Origin2000 system (two processors and an I O unit) Pong, et al. used the Mur [21] formal verification system to verify an ....

....10 Figure 9: The markers inserted in the stimulus from the witness string shown in Figure 8. Quiescent E1(X:ShClean) Read(Y) on vc0 from P1 [13] E1 sending PInvalidate(X) to P1 [14] E1 sending MDrop(X) to M1 [15] E1 sending MRead(Y) to M2 [16] E1(Y:PendingReq) ReadExclResp(Y) on vc1 from M2 [17] E1 sending PReadResp(Y) to P1 [18] Quiescent to the cache coherence engine in the E chip. Soon, we will be using this approach to verify the cache coherence engine at the memory directory (the M chip) 6 Conclusion It is commonplace in ....

Asgeir Th. Eir iksson, John Keen, Alex Silbey, Swami Venkataraman, and Michael Woodacre. Origin system design methodology and experience: 1m-gate asics and beyond. In COMPCON-97, 1997.

....Verilog test bench. We establish lower and upper bounds on the performance of the Raven environment executing on a single processor, on a set of distributed processors, and on a shared memory multiprocessor. 1 Introduction Contemporary multiprocessors, such as the Cray T3E [2] and the SGI Origin [3, 4], have tens of millions of gates per node. This complexity makes the verification of the design a very problematic and time consuming endeavor. This verification problem is rooted in the exponential growth of IC technology. As design complexity and integration increase, the verification challenges ....

Asgeir Th. Eir iksson, John Keen, Alex Silbey, Swami Venkataraman, and Michael Woodacre, "Origin System Design Methodology and Experience: 1M-gate ASICs and Beyond," COMPCON-97.

....program execution. Obviously, it is impossible to conclude that, if the system is correct for a given program execution, it must be correct for all executions and all programs. More recently, formal verification methods have been used to validate the coherence protocol of the SGI Origin2000 [15, 16, 17] and the Sun S3.mp (Sun Scalable Shared Memory Multiprocessor) 18, 19] Eir iksson used the Symbolic Model Verifier (SMV) 20] to verify an abstract model of a three node Origin2000 system (two processors and an I O unit) Pong, et al. used the Mur [21] formal verification system to verify ....

....[24, 25] which is built around the C C language. Figure 9: The markers inserted in the stimulus from the witness string shown in Figure 8. Quiescent E1(X:ShClean) Read(Y) on vc0 from P1 [13] E1 sending PInvalidate(X) to P1 [14] E1 sending MDrop(X) to M1 [15] E1 sending MRead(Y) to M2 [16] E1(Y:PendingReq) RExclResp(Y) on vc1 from M2 [17] E1 sending PReadResp(Y) to P1 [18] Quiescent The witness strings from the Mur formal verification are post processed into stimulus encoded as Raven apply( and verify( calls. As an example, Figure 8 shows a snippet from a witness ....

Asgeir Th. Eir iksson, John Keen, Alex Silbey, Swami Venkataraman, and Michael Woodacre. Origin system design methodology and experience: 1m-gate asics and beyond. In COMPCON-97, 1997.

....Unfortunately, it provides little assistance in the development of new hardware. Furthermore, ARCHTEST is unable to detect deadlock, live lock, and loss of data coherence. More recently, formal verification methods have been used to validate the coherence protocol of the SGI Origin2000 [28, 29, 30] and the Sun S3.mp (Sun Scalable Shared Memory Multiprocessor) 31, 32] Eir iksson used the Symbolic Model Verifier (SMV) 33] 10 to verify an abstract model of a three node Origin2000 system (two processors and an I O unit) Pong, et al. used the Mur [13] formal verification system to verify ....

Asgeir Th. Eir iksson, John Keen, Alex Silbey, Swami Venkataraman, and Michael Woodacre. Origin system design methodology and experience: 1m-gate asics and beyond. In COMPCON-97, 1997.

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Asgeir Th. Eirksson, John Keen, Alex Silbey, Swami Venkataraman, and Michael Woodacre. Origin system design methodology and experience: 1m-gate asics and beyond. In COMPCON-97, 1997.

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