Dennis Abts and Mike Roberts. Verifying large-scale multiprocessors using an abstract verication environment abstract verification environment. In Proceedings of the 36th Design Automation Conference (DAC99), pages 163--168, June 1999.  Home/Search   Document Not in Database   Summary   Related Articles   Check

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Dennis Abts and Mike Roberts. Verifying large-scale multiprocessors using an abstract verication environment abstract verification environment. In Proceedings of the 36th Design Automation Conference (DAC99), pages 163--168, June 1999.

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D. Abts and M. Roberts, "Verifying large-scale multiprocessors using an abstract verification environment", In Proceedings of the 36 Design Automation Conference (DAC 99), pages 163-68, June 1999.

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D. Abts and M. Roberts. Verifying large-scale multiprocessors using an abstract verification environment. In Proceedings of the 36th Design Automation Conference (DAC99), pages 163--168, June 1999.

No context found.

D. Abts and M. Roberts, "Verifying large-scale multiprocessors using an abstract verification environment", In Proceedings of the 36 Design Automation Conference (DAC 99), pages 163-68, June 1999.

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D. Abts and M. Roberts, "Verifying large-scale multiprocessors using an abstract verification environment", In Proceedings of the 36 Design Automation Conference (DAC 99), pages 163-68, June 1999.

....The low level (detailed) view of the design which the logic simulator provides is a mixed blessing since we have very limited techniques available to verify abstract properties, such as write serialization, at such a low level. To remedy this situation, elaborate verification environments [26] can be constructed to hide this detail allowing us to reason about design correctness at a more abstract level. Unfortunately, logic simulation, by itself, does not solve the verification problem. We are left guessing how much simulation is really enough, and how to generate the interesting ....

....pieces of the design such as a memory arbiter that is responsible for guaranteeing the order of memory references in the system, for instance. Traditional logic simulators with coverage analysis tools (to quantify when we are done simulating) combined with abstract verification environments [26] are still important to verify the RTL implementation of the memory system. 8 Conclusions The design and verification of cache coherent memory systems is a daunting task. We have established a set of sufficient conditions for determining the correctness of the memory coherence and consistency ....

D. Abts and M. Roberts. Verifying large-scale multiprocessors using an abstract verification environment. To appear in the proceedings of the 36th annual Design Automation Conference (DAC).

....to the hardware (i.e. test vectors) are inadequate tools for reasoning about the correctness of complex architectural features, such as cache coherence protocols and memory consistency models. Similarly, model checkers offer very limited utility on such large designs. We have previously proposed [1] a novel verification framework, called Raven, that addresses many of these challenges. In this paper, we examine the performance implications of verifying systems at higher levels of abstraction. A detailed performance analysis is conducted to compare this higherlevel approach against an ....

....(sockets) IPC Logic Simulator Raven Diagnostic (b) The diagnostic program and logic simulator use sockets for interprocess communication. Figure 1: The Raven verification environment. large scale multiprocessor systems. To address these challenges, we have previously proposed Raven [1] as a framework upon which complex, self checking diagnostics can be constructed using a modern programming language such as C . Raven consists of two libraries: the Diagnostic Programming Interface (DPI) which is a user level library that is linked with the diagnostic program, and a ....

Dennis Abts and Mike Roberts, "Verifying Large-Scale Multiprocessors Using an Abstract Verification Environment, " Proceedings of the 36th Annual Design Automation Conference, pp. 163--168, June 1999.

....the witness strings generated by the Mur formal verification on the Verilog RTL implementation of the hardware. The Verilog is compiled and simulated using an internally developed tool called Gensim [23] The witness strings are encoded using a high level verification environment called Raven [24, 25], which is built around the C C language. The witness strings from the Mur formal verification are post processed into stimulus encoded as Raven apply( and verify( calls. As an example, Figure 8 shows a snippet from a witness string as generated by the Mur formal verification tool. This ....

D. Abts and M. Roberts. Verifying large-scale multiprocessors using an abstract verification environment. In Proceedings of the 36th Design Automation Conference (DAC99), pages 163--168, June 1999.

....to the hardware (i.e. test vectors) are inadequate tools for reasoning about the correctness of complex architectural features, such as cache coherence protocols and memory consistency models. Similarly, model checkers offer very limited utility on such large designs. We have previously proposed [1] a novel verification framework, called Raven, that addresses many of these challenges. In this paper, we examine the performance implications of verifying systems at higher levels of abstraction. A detailed performance analysis is conducted to compare this higherlevel approach against an ....

....the correctness of a cache coherence protocol or a memory consistency model [5] Clearly, discrete event logic simulators by themselves are ill equipped to handle the verification challenges posed by large scale multiprocessor systems. To address these challenges, we have previously proposed Raven [1] as a frameSimula t io n Kernel Wrap p e r i c D o s t Prog r a m a i n g I P C D P I Logic Ke e D i a o ti c s n g n r l (a) A layered approach provides increasing levels of abstraction much like the way a network protocol stack, or operating system shields the user level ....

Dennis Abts and Mike Roberts, "Verifying Large-Scale Multiprocessors Using an Abstract Verification Environment, " Proceedings of the 36th Annual Design Automation Conference, pp. 163--168, June 1999.

.... witness strings generated by the Mur formal verification on the Verilog RTL implementation of the hardware. The Verilog is compiled and simulated using an internally developed tool called Gensim [23] The witness strings are encoded using a high level verification environment called Raven [24, 25], which is built around the C C language. Figure 9: The markers inserted in the stimulus from the witness string shown in Figure 8. Quiescent E1(X:ShClean) Read(Y) on vc0 from P1 [13] E1 sending PInvalidate(X) to P1 [14] E1 sending MDrop(X) to M1 [15] E1 sending MRead(Y) to M2 [16] ....

D. Abts and M. Roberts. Verifying large-scale multiprocessors using an abstract verification environment. In Proceedings of the 36th Design Automation Conference (DAC99), pages 163--168, June 1999.

....the witness strings generated by the Mur formal verification on the Verilog RTL implementation of the hardware. The Verilog is compiled and simulated using an internally developed tool called Gensim [19] The witness strings are encoded using a high level verification environment called Raven [20, 21], which is built around the C C language. The witness strings from the Mur formal verification are post processed into stimulus encoded as Raven apply( and verify( calls. As an example, Figure 11 shows a snippet from a witness string as generated by the Mur formal verification tool. This ....

D. Abts and M. Roberts. Verifying large-scale multiprocessors using an abstract verification environment. In Proceedings of the 36th Design Automation Conference (DAC99), pages 163--168, June 1999.

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