A. Chowdhary, S. Kale, P. Saripella, N. Sehgal, R. Gupta, A General Approach for Regularity Extraction in Datapath Circuits, Proceedings of the International Conference on Computer-Aided Design, 1998, pp. 332-339.  Home/Search   Document Details and Download   Summary   Related Articles   Check

.... extraction attempts to find common sub structures (templates) in one or a collection of circuits (graphs) There are many applications for regularity extraction, including, but not limited to, scheduling during logic synthesis [1] system level partitioning [2] and FPGA mapping and placement [3]. We aim to build a general profiling technique for simultaneous template generation and matching, which is applicable to any task that uses a directed labeled graph. We target the generation and matching algorithm towards instruction generation and selection, though the methods we present are ....

A. Chowdhary, S. Kale, P. Saripella, N. Sehgal and R. Gupta, A General Approach for Regularity Extraction in Datapath Circuits, International Conference on Computer-Aided Design, 1998.

....of other CAD applications. Templates are used during scheduling to address timing constraints and hierarchical scheduling [9] Datapath circuits exhibit a high amount of regularity; hence regularity extraction reduces the complexity of the program as well as increasing the quality of the result [10,11]. System level partitioning is yet another use of regularity extraction [12] Furthermore, proper use of templates can lead to low power designs [13] In the next section, we discuss related work. Then, in Section 3, we formalize the problem of template matching and generation. Section 4 proposes ....

....[14] wherein a greedy, bottom up procedure for a silicon compiler is described. Keutzer [15] modeled a system as a DAG and heuristically partitioned it to yield rooted trees and applied compiler techniques to test for pattern matches. Trees and single output templates are used by Chowdhary et al. [10] to cover datapath circuits. Rao and Kurdahi [12] addressed template generation for systemlevel clustering using the well known first fit approach to bin filling. More recently, Cadambi and Goldstein [8] propose single output template generation via a constructive, bottom up approach. Both ....

A. Chowdhary, S. Kale, P. Saripella, N. Sehgal and R. Gupta, A General Approach for Regularity Extraction in Datapath Circuits, Proc. of International Conference on ComputerAided Design, 1998.

.... growing templates by using hints from bus names and datapath features such as high fanout control nets [1] A more structured heuristic is based on identifying tree templates and single principal output templates, where all outputs of a template are in the transitive fanin of a particular output [2]. Clustering, where a group of nodes are clustered around an initial node(s) is yet another approach to template generation [9, 1, 6] Other approaches to extracting circuit regularity assume a given set of templates [10, 3] The novelty of our approach to template generation and circuit ....

A. Chowdhary, S. Kale, P. Saripella, N. Sehgal, and R. Gupta. "A General Approach for Regularity Extraction in Datapath Circuits". In IEEE International Conference on Computer-Aided Design, pages 332--339, 1998.

.... growing templates by using hints from bus names and datapath features such as high fanout control nets [1] A more structured heuristic is based on identifying tree templates and single principal output templates, where all outputs of a template are in the transitive fanin of a particular output [2]. The novelty of our approach to template generation is due to decomposing the circuit graph prior to identifying the templates into a hierarchy of subgraphs called clans. The hierarchy forms a parse tree of the graph: the leaf nodes are gates in the netlist; intermediate nodes correspond to ....

....the algorithm to an n bit ripple adder, and we are able to identify separate templates that represent the carry and sum logic. We ve also applied it to a 4 bit ALU [7] and we identified 3 templates that cover each bit slice. In addition, we applied it to the 4 Theta 4 multiplier described in [2], and we are able to identify two templates each repeating 12 times. Choosing (instantiating) an appropriate subset of the templates to cover the entire circuit graph is a binate covering problem, which can be solved using efficient binate solvers such as Scherzo [3] The covering constraints ....

A. Chowdhary, S. Kale, P. Saripella, N. Sehgal, and R. Gupta. "A General Approach for Regularity Extraction in Datapath Circuits". In IEEE International Conference on ComputerAided Design, pages 332--339, 1998.

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A. Chowdhary, S. Kale, P. Saripella, N. Sehgal, R. Gupta, A General Approach for Regularity Extraction in Datapath Circuits, Proceedings of the International Conference on Computer-Aided Design, 1998, pp. 332-339.

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A. Chowdhary et al, "A General Approach for Regularity Extraction in Datapath Circuits", Proc. of ICCAD, 1998.

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Amit Chowdhary, Sudhakar Kale, Phani Saripella, Naresh Sehgal, and Rajesh Gupta. A general approach for regularity extraction in datapath circuits. In Computer-Aided Design (ICCAD), pages 332--339, 1998.

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