D. Lenosky, J. Laudon, K. Gharachorloo, A. Gupta, and J. Hennessy. The directory-based cache coherence protocol for the DASH multiprocessor. In Proc. 17th International Symposium on Computer Architecture, pages 148--159, May 1990.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....and writable copies of each memory line for multiprocessors. Modification of one copy of a datum may require updating of other copies to maintain consistency among them. Several coherence protocols have been proposed for distributed multiprocessor architectures but few are formally verified [1, 15, 2, 10]. This research was supported by the Advanced Research Projects Agency through NASA grant NAG 2 891. Formal verification is desirable because there could be subtle bugs as the complexity of protocols increases. Although finite state methods (e.g. 3, 5] can solve many verification problems ....

D. Lenosky, J. Laudon, K. Gharachorloo, A. Gupta, and J. Hennessy. The directory-based cache coherence protocol for the DASH multiprocessor. In Proc. 17th International Symposium on Computer Architecture, pages 148--159, May 1990.

....using distributed directories with a limited number of pointers. Pointer overflows are handled by a protocol with a directory organized as singly linked lists. Every memory block is associated with a home node which is the node where the physical memory page containing the memory block resides [9]. The home node serializes concurrent requests to the block and maintains a pointer to the head node of the linked list. Part of the physical memory at each node is allocated as a large InterNode Cache (INC) A copy of every cache block retrieved from remote nodes is loaded into the INC. This ....

Lenosky, D., et al., "The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor", Proc. of the 17th Int'l Symposium on Computer Architecture, June 1990, pp. 148-159.

....provided by a cache coherence protocol which defines a set of rules coordinating processors, cache controllers, and memory controllers. The verification of cache coherence protocols is an important subject which has been neglected for a long time. Many protocols have been proposed and implemented [6, 16, 30, 46, 57, 61, 88]; however, their correctness has never been formally validated. The main reason for this state of affair is that most existing protocols are relatively simple snooping protocols which use broadcast of updates or invalidations to keep data copies consistent. Their correctness can be established by ....

....affair is that most existing protocols are relatively simple snooping protocols which use broadcast of updates or invalidations to keep data copies consistent. Their correctness can be established by careful inspection, thorough analysis [7, 80] or simple techniques such as testing and simulations [35, 61]. The lack of efficient verification tools is also a reason. However, the need for high performance and scalable machines has made cache protocols much more complex today than before. As faster, larger systems are designed and built, the complexity of cache protocols will continue to increase. It ....

[Article contains additional citation context not shown here]

Lenosky, D., Laudon, J., Gharachorloo, K., Gupta, A. and Hennessy, J., "The DirectoryBased Cache Coherence Protocol for the DASH Multiprocessor", Proc. of the 17th Int'l Symposium on Computer Architecture, pp. 148-159, June 1990.

....protocol errors due to implementation details not covered by formal protocol models. However, since its error coverage relies on the ability to exercise all protocol interactions, testscript design becomes an important factor. Unlike previous simulation approaches to protocol validation (see e.g. [7]) the uniqueness of our methodology lies in the way in which it detects an error and guides the protocol designer to find the protocol error. We will specifically focus on this aspect in the following. 6.1. Architectural Simulation Model The architectural model differs from the one in Section ....

Lenosky, D., et al., "The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor", Proc. of the 17th Int'l Symposium on Computer Architecture, June 1990, pp. 148-159.

....cability is inherently limited to systems with an interconnection supporting efficient broadcast, mostly shared bus systems. Unfortunately a shared bus is non scalable in the sense that a few processors can saturate it even in the presence of private caches. By contrast, directory based protocols [1, 4, 7, 17] are more appropriate for systems with very large numbers of processors. By associating every memory block with a directory entry keeping track of caches with a copy of the block, coherence messages are sent to individual processors rather than broadcast to all processors, removing the need for an ....

....the protocol behavior is often hard to predict [2] because the protocol designer can not visualize all possible temporal interleavings of coherence messages. In general, a directory protocol can be greatly simplified if the interconnection network is FIFO (First In First Out) between any two nodes [17]. To illustrate why, consider the following simple case of a processor first sending the copy of a dirty block to memory on a replacement (write back) and then, immediately afterwards, accessing the block again and sending a request for the block to memory (miss) If the network is not FIFO the ....

[Article contains additional citation context not shown here]

Lenosky, D., et al., "The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor ", Proc. of the 17th Int'l Symposium on Computer Architecture, June 1990, pp. 148-159.

....bandwidth requirements and improve remote access latency. Therefore, cache coherence has to be enforced both inside an HPAM level and among different levels. Cache coherence solutions that use a combination of different protocols (snoopy and directory based) have been proposed and implemented [6] for homogeneous DSMs, and can be reused in an HPAM context. However, an HPAM machine can take advantage of coherence solutions that exploit its heterogeneous nature. In this paper, the potential advantages of having multiple line sizes across the hierarchy are studied. Similar to conventional ....

Lenosky, D. and Laudon, J. and Gharacharloo, K. and Gupta, A. and Hennessy, J. The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor. In Proc. of the 17th Annual Int. Symp. on Computer Architecture, May 1990.

....remote node is performed by short message transfers between the local node and the remote node. Maintaining global cache coherence is possible but an orthogonal issue for the DI based systems, although each node has locally coherent caches. 5 Either hardware directory based coherence protocols [2, 26] or software coherence schemes [7, 11] can be used to provide a cache coherent shared address space. Internode Synchronization A node can communicate with other nodes with message passing. In DI multicomputer, short and long messages use different mechanisms for synchronization as they are ....

....not an on chip FIFO as in the DI multicomputer. This means that incoming short messages still need to be fetched from memory, increasing the latency. The issue of implementing global cache coherence is an orthogonal issue to the DI based systems. Either hardware directory based coherence protocols [2, 26] or software based approaches [7, 11] can be implemented on top of the DI based systems to support the cache coherence. 9 Summary The DI multicomputer uses dynamic interconnection and novel message handling mechanisms to increase in memory bandwidth and reduce message passing overhead. Dynamic ....

D., Laudon, J., Gharachorloo, K., Gupta, A., and Hennessy, J. The Directory-Based Cache Coherence Protocol for the DASH Computer. In Proceedings of the 17th Annual International Symposium on Computer Architecture, pp. 148--159, May 1990.

....creating a real possibility of design errors, especially for those used in large scale multiprocessor systems. Formal verification is desirable because the bugs can be quite subtle and hard to capture by simulation. Several coherence protocols have been proposed but few are formally verified [4, 67, 9, 47]. One of the effective ways to validate protocols is using finite state methods (model checking) Finite state methods enumerate the states of the reachable state graph of the system, searching for states that violate a specified property (e.g. Mur [15] SMV [21] SPIN [34] COSPAN [38] These ....

....and writable copies of each memory line for multiprocessors. Modification of one copy of a datum may require updating of other copies to maintain consistency among them. Several coherence protocols have been proposed for distributed multiprocessor architectures but few are formally verified [4, 5, 67, 9, 47]. Formal verification is very important because there could be subtle design errors as the complexity of protocols increases, especially for large scale multiprocessor systems. Finite state methods (e.g. 15, 21, 34, 38] have been used to validate some cache coherence protocols, including Gigamax ....

D. Lenosky, J. Laudon, K. Gharachorloo, A. Gupta, and J. Hennessy. The directory-based cache coherence protocol for the DASH multiprocessor. In Proc. 17th International Symposium on Computer Architecture, pages 148--159, May 1990.

No context found.

Lenosky, D. and Laudon, J. and Gharacharloo, K. and Gupta, A. and Hennessy, J. The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor. In Proc. of the 17th Annual Int. Symp. on Computer Architecture,May 1990.

No context found.

Lenosky, D., et al., "The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor", Proc. of the 17th Int'l Symposium on Computer Architecture, June 1990, pp. 148-159.

No context found.

D. Lenowski, J. Laudon, K. Gharachorloo, A. Gupta, and John Hennessy. The directory-based cache coherence protocol for the DASH multiprocessor. In 17th International Symposium on Computer Architecture. ACM, 1990.

No context found.

D. Lenowski, J. Laudon, K. Gharachorloo, A. Gupta, and John Hennessy. The directory-based cache coherence protocol for the DASH multiprocessor. In 17th International Symposium on Computer Architecture. ACM, 1990.

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