SPARC International. The SPARC Architecture Manual Version 8. Prentice-Hall, Englewood Cliffs, New Jersey, 1992.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....mechanisms in the processors are not assumed for the above techniques, and they are thus applicable to all computers. The following mechanisms are useful for the high speed implementation of the MBCF, and take advantage of special features of the latest, most advanced processors (e.g. SuperSPARC [24, 67] and UltraSPARC [70, 81] ffl TLB corresponding to coexistence of multiple contexts Each entry in the translation look aside buffer (TLB) of a recent processor has a field for a context identifier (context ID) and the OS for the processor can switch contexts without clearing entries from the ....

....hub connection for 100BASE TX non switching hub connection for 10BASE T switching hubs were also used for 100BASE TX and 10BASE T 72 non switching hubs were used in the following measurements unless otherwise specified. 3 supports the SuperSPARC processor (SPARC V8 [67] architecture) This section is a report on various aspects of the performance of the MBCF Ether protocol on a real system, including the overheads incurred by using MBCF Ether. Most of the results fluctuate to a greater or lesser degree according to the situation of the processor caches and of ....

SPARC International, Inc. The SPARC Architecture Manual Version 8, 1992.

....high level instruction for a sequence of assembly instructions. During the parsing of assembly code, machine idioms are checked for, in order to remove particularities of the machine itself. In the case of SPARC, most of the idioms relate to the synthetic instructions described in the SPARC manual [17]; we replace such instructions by more expressive ones. For example, the increment instruction is replaced by an addition instruction with explicit operands rather than implicit ones, and a subtract with carry using destination register g0 is replaced with a compare instruction (as register g0 ....

....on RISC machines due to the stylized code fragments that compilers generate for indexed jumps. In contrast, CISC code is much harder to analyse for indexed jumps. The generation of the CFG needs to remove dependencies on the hardware pipeline by analysing delayed instructions. On SPARC [17], instructions that transfer flow of control work in combination with the next instruction; the delayed instruction. The delayed instruction may or may not be executed based on the type of branch. If enabled, it is executed prior to the target of the branch being reached. This semantic behaviour ....

[Article contains additional citation context not shown here]

Sparc International, Menlo Park, California. The SPARC Architecture Manual -- Version 8, 1992.

....requires changes to the stack pointer. For short values of n (those that fit in 13 bits) the following prologues, new reg win and same reg win describe the most common callee prologues. Also note that a procedure may not have a prologue at all, as in the case of a leaf procedure (see page 198 of [5]) in which case a stack space is not allocated at all. CALLEEPROLOGUE newregwin locals IS SAVE ( SP, imode(locals) SP) CALLEEPROLOGUE sameregwin locals IS ADD ( SP, imode(locals) SP) On Pentium, the most common callee prologue sets up the frame base pointer and the stack pointer, as well ....

SPARC International Inc. The SPARC Architecture Manual -- Version 8. Prentice Hall, Englewood Cliffs, New Jersey 07632, 1992.

....Impact [34] and International Business Machines RISC System 6000 model 43P [17] In the rest of the paper we will refer to these systems by means of the name of their manufacturers, namely SUN, HP, DEC, SGI and IBM. The reference systems are based on five different CPUs, namely SuperSPARC [37][39] HPPA 7150 [15] 2] DECchip 21064 (Alpha) 6] 26] MIPS R4400 [12] and PowerPC 604 [36] which cover the two directions of instruction level parallelism, i.e. pipelining and scalarity, and feature different memory hierarchy organization. Table 1 summarizes the characteristics of the ....

SPARC International Inc., The SPARC Architecture Manual Version 8, - Prentice Hall, 1992.

....the machine instruction set it was written for. Computer architecture manuals describe the syntax and semantics of machine instructions by a combination of natural language and ISP (Instruction Set Processor notation) descriptions, for example see Intel s Pentium manual [6] and SPARC s V8 manual [12]. The syntax of the instructions in assembly and its associated binary or machine code is well defined in the manual in the form of tables. ISP is a high level notation that resembles a structured programming language, with constructs for conditionals and iteration. The notation itself does not ....

Sparc. The SPARC Architecture Manual -- Version 8. Sparc International, Menlo Park, California, 1992.

....generates code to decode binary instructions and simulate their behavior. Architecture descriptions in Facile are compact, reducing the opportunity for error, and are similar to some descriptions found in architecture manuals. Architecture manuals, such as the one for SPARC Version 9 [78], often use tables to describe the binary encodings of several instructions simultaneously. Facile, like Ramsey and Fernandez s architecture description language, can describe instruction encodings in similar tables (see Figure 4.2) This approach should reduce errors by making descriptions in ....

SPARC International, Inc., The SPARC Architecture Manual Version 9, edited by David L. Weaver and Tom Germond, PTR Prentice Hall, 1994.

....proposed designs. In section 5 the TLB and cache simulation results are presented and analyzed. Finally, we detail our conclusions in section 6. 2 Related Work Limited support for multiple page size TLBs can be found in many of the current CPU designs. e.g. MIPS R4000 [8] SPARC Reference MMU [11] and DEC Alpha [20] The SPARC reference MMU provides for pages of 4KB, 256KB, 16MB and 4GB. The page size is determined by the position of the leaf page entry within a forward mapped page table. In the MIPS design the page size is determined by a bit mask. Specialized allocation of large pages ....

SPARC International Inc. The SPARC Architecture Manual version 8. Prentice Hall, 1992.

....high level instruction for a sequence of assembly instructions. During the parsing of assembly code, machine idioms are checked for, in order to remove particularities of the machine itself. In the case of SPARC, most of the idioms relate to the synthetic instructions described in the SPARC manual [20]; we replace such instructions by more expressive ones. For example, the increment instruction is replaced by an addition instruction with explicit operands rather than implicit ones, and a subtract with carry using destination register g0 is replaced with a compare instruction (as register g0 ....

....on RISC machines due to the stylized code fragments that compilers generate for indexed jumps. In contrast, CISC code is much harder to analyse for indexed jumps. The generation of the CFG needs to remove dependencies on the hardware pipeline by analysing delayed instructions. On SPARC [20], instructions that transfer flow of control work in combination with the next instruction; the delayed instruction. The delayed instruction may or may not be executed based on the type of branch. If enabled, it is executed prior to the target of the branch being reached. This semantic behaviour ....

[Article contains additional citation context not shown here]

Sparc International, Menlo Park, California. The SPARC Architecture Manual -- Version 8, 1992.

....requires changes to the stack pointer. For short values of n (those that fit in 13 bits) the following prologues, new reg win and same reg win describe the most common callee prologues. Also note that a procedure may not have a prologue at all, as in the case of a leaf procedure (see page 198 of [5]) in which case a stack space is not allocated at all. CALLEEPROLOGUE newregwin locals IS SAVE ( SP, imode(locals) SP) CALLEEPROLOGUE sameregwin locals IS ADD ( SP, imode(locals) SP) On Pentium, the most common callee prologue sets up the frame base pointer and the stack pointer, as well ....

SPARC International Inc. The SPARC Architecture Manual -- Version 8. Prentice Hall, Englewood Cliffs, New Jersey 07632, 1992.

....flow graph for each procedure, and a high level opcode for each instruction. However, during the parsing of the code, machine idioms are checked for in order to remove particularities of the machine itself. Most of these idioms relate to the synthetic instructions described in the SPARC manual [13]; we replace such instructions by more expressive ones. For example, the increment instruction is replaced by an addition instruction with explicit operands rather than implicit ones, and a subtract with carry using destination register g0 is replaced by a compare instruction (as register g0 is ....

....on RISC machines due to the stylized code fragments that compilers generate for indexed jumps. In contrast, CISC code is much harder to analyse for indexed jumps. The generation of the control flow graph removes dependencies on the hardware pipeline, by analysing delayed instructions. On SPARC [13], instructions that transfer flow of control work in combination with a delayed instruction (that follows it in the assembly code) The transfer instruction is first checked to determine if a branch is to be taken or not, and the delayed instruction is executed before the flow of control is ....

Sparc. The SPARC Architecture Manual -- Version 8. Sparc International, Menlo Park, California, 1992.

....copying collector, many threads allocate objects in to space at the same time. One approach to managing this concurrency would be for each thread to increment the copy pointer atomically for each object it copies, using some hardware operation such as fetch and add or compare and swap (CAS) [3]. However, our experiments indicate that this results in too much contention. The alternative we adopted was to have each thread use such atomic allocation only to allocate relatively large regions called local allocation bu#ers (LABs) A thread can then do local allocations within this bu#er with ....

The SPARC Architecture Manual Version 9, Sun Microsystems, Inc.

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SPARC International, Inc. The SPARC Architecture Manual - Version 8, Prentice-Hall, Englewood Cliffs, New Jersey, 1992.

.... fully support integer math instructions (specifically, signed and unsigned multiply divide remainder) that previously were not (i.e. on sun4 and sun4c as mentioned above) Most sun4m machines use the SPARC Reference Memory Management Unit (SRMMU) as described in the SPARC Architecture Manual [1]. This is basically just a 3 level MMU page table scheme, again with contexts just like the sun4c. The difference here is that the MMU directly reads the kernel software page tables in physical ram to perform a translation. So people familiar with the MMU found on the Intel x86 processors can ....

The SPARC Architecture Manual Version 8. SPARC International. Prentice Hall, 1992.

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SPARC International. The SPARC Architecture Manual Version 8. Prentice-Hall, Englewood Cliffs, New Jersey, 1992.

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SPARC International. The SPARC architecture manual: Version 8. Prentice-Hall, 1992.

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Menlo Park and SPARC International. The SPARC Architecture Manual Version 8. Prentice Hall, 1992. ISBN 0-13-825001-4.

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SPARC International. The SPARC Architecture Manual: Version 8. Prentice-Hall, 1992.

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SPARC International. The SPARC architecture manual: Version 8. Prentice-Hall, 1992.

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"The SPARC Architecture Manual: Version 8", Prentice Hall, ISBN 0-13-825001-4.

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SPARC International. The SPARC architecture manual: Version 8. Prentice-Hall, 1992.

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SPARC International. The SPARC architecture manual: Version 8. Prentice-Hall, 1992.

No context found.

"The SPARC Architecture Manual: Version 8", Prentice Hall, ISBN 0-13-825001-4.

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SPARC International. The SPARC architecture manual: Version 8. Prentice-Hall, 1992.

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"The SPARC Architecture Manual: Version 8", Prentice Hall, ISBN 0-13-825001-4.

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SPARC International, Inc. The SPARC Architecture Manual Version 8, 1992.

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