S.-Y. Huang, K.-T. Cheng and K.-C. Chen, "Incremental Logic Rectification," Proc. IEEE VLSI Test Symp., Monterey, CA, pp. 455-460, Apr. 1997.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....model or there is no guarantee that they will find a correct solu tion even if one exists. Therefore, we need a tool that is applicable to large circuits and is accurate enough to rectify multiple design errors. A hybrid technique using both simulation and symbolic algorithm has been suggested [11]. But it requires the existence of a gate level model for both the specification and the implementation with significant structural similarity. In the next section, we present a simulationbased procedure for correcting multiple design errors in large circuits, which does not rely on structural ....

....our diagnosis procedure that it takes less time to consider many suspects than to further prune the suspect list. The correction time is small since in most cases the first suspect is used for correction. The total time is less than the corresponding time for the symbolic error correction tool ET [11]. Note that our time does not include the time to reverified the corrected circuit. Results for diagnosis and correction of multiple random errors are shown in Table 2. Each entry is the average of two runs. The entries with no corrections occurred when the tool was terminated after one hour ....

S.-Y. Huang, K.-T. Cheng and K.-C. Chen, "Incremental Logic Rectification," Proc. IEEE VLSI Test Symp., Monterey, CA, pp. 455-460, Apr. 1997.

....procedure is applied. This is undesirable as it 25 can jeopardize some of the engineering e#ort already invested in the design. In the problem of Engineering Change, one is interested in the least amount of re synthesis on the existing design to obtain one that satisfies the new specification [5, 11, 12, 17]. Depending upon the information available, two versions for engineering change can arise. For each version, a fundamentally di#erent solution is developed. In the first version, a naming equivalence (i.e. functional equivalence) between signals of the new and old specification and the existing ....

....engineering change can arise. For each version, a fundamentally di#erent solution is developed. In the first version, a naming equivalence (i.e. functional equivalence) between signals of the new and old specification and the existing design is available from the synthesis process. Existing work [5, 11, 12], uses this information to re synthesize the signals that are not functionally equivalent. In the second version [17] such a naming correspondence is not available as the old and new specification can only provide primary output responses in terms of the primary input stimuli. It is reported by ....

S. Y. Huang, K. C. Chen and K. T. Cheng, "Incremental logic rectification," in Proc. of IEEE VLSI Test Symp., pp. 143--149, 1997. 28

....In these cases, design error diagnosis and logic rectification is needed. Automatic error diagnosis and correction save a lot of design debugging time. Existing logic rectification approaches can be classified into several categories: error model based approaches [2 5] structural approaches [6 8], and re synthesis based approaches [911 ] In error model based approaches, after error diagnosis, the implementation is rectified by matching the error with an error type in the model. The method is relatively restricted because it may fail in error cases not covered by the model. In this ....

S.-Y. Huang, K.-C. Chen, K.-T. Cheng. Incremental Logic Rectification. Proc. of VLSI Test Symposium, 1997, pp. 134-139.

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