R. Esser and R. Knecht. Intel Paragon XP/S -- architecture and software environment. Technical Report KFA-ZAM-IB-9305, 1993.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....clean open platform to explore alternatives. The problem we must tackle is strikingly similar to that of building e#cient network interfaces, which also must maintain a large number of concurrent flows and juggle numerous outstanding events [20] This has been tackled through physical parallelism [21] and virtual machines [27] We tackle it by building an extremely e#cient multithreading engine. As in TAM [22] and CILK [23] it maintains a two level scheduling structure, so a small amount of processing associated with hardware events can be performed immediately while long running tasks are ....

R. Esser and R. Knecht. Intel Paragon XP/S -- architecture and software environment. Technical Report KFA-ZAM-IB-9305, 1993.

....processors. Therefore, several recent MIMD architectures explicitly designed to support data parallel languages (HPF and C , usually) have been equipped with specific hardware mechanism to optimize this function. It is in particular the case with the CM 5 [33] of Thinking Machine and the Paragon [11, 21] of Intel. MIMD architectures with an optimized global synchronization hardware facility are sometimes (somewhat improperly, see below) called SPMD (Single Program Multiple Data) as they are specifically designed to execute data parallel languages efficiently. A better nickname would probably be ....

R. Esser and R. Knecht. Intel Paragon XP/S -- architecture and software environment. Technical Report KFAZAM -IB-9305, Central Institute for Mathemantics, Research Center Juelich, 1993.

....clean open platform to explore alternatives. The problem we must tackle is strikingly similar to that of building e#cient network interfaces, which also must maintain a large number of concurrent flows and juggle numerous outstanding events [20] This has been tackled through physical parallelism [21] and virtual machines [27] We tackle it by building an extremely e#cient multithreading engine. As in TAM [22] and CILK [23] it maintains a two level scheduling structure, so a small amount of processing associated with hardware events can be performed immediately. The execution model is similar ....

R. Esser and R. Knecht. Intel Paragon XP/S -- architecture and software environment. Technical Report KFA-ZAM-IB-9305, 1993.

....sending threshold examples from one processor to an other. 14 3.4.3 Experimental results Our target machine is an Intel Paragon with 30 nodes. Briefly, it is a distributed memory machine in which i860 processors are connected on a grid. A complete description of its architecture can be found in [4]. To obtain good performances and a good scalability, libraries are used for communications (BLACS) and for computations (level 1 BLAS) Figure 7 presents the different execution times for both versions I and II. The execution time is lower for version I than for version II. However, as this last ....

R. Esser and R. Knecht. Intel Paragon XP/S - Architecture and Software Environment. Technical Report KFA-ZAM-IB-9305, Central Institute for Applied Mathematics, Research Center Julich (KFA), April 1993.

.... Examples include Vesta [7] and the nCUBE system software [8] Recent studies show that various simple partitioning schemes do indeed account for most of observed parallel I O patterns [24] In addition to the commercial offerings (IBM SP2 PIOFS [6] Intel iPSC CFS [25, 27] and Paragon PFS [11, 28], nCUBE [8] and Thinking Machines CM 5 sfs [2, 20] there has been a recent flurry of activity in the research community. PIOUS [22, 23] and PETSc Chameleon I O [14] are both widely available nonproprietary portable parallel I O interfaces. PIOUS is a PVM based parallel file interface. Files can ....

Rudiger Esser and Renate Knecht. Intel Paragon XP/S --- architecture and software environment. Technical Report KFA-ZAM-IB-9305, Central Institute for Applied Mathematics, Research Center Julich, Germany, April 1993.

....its size and the needed accuracy for the simulation results lead to high performance requirements for the executing simulator, creating a need for parallel simulation as a means to reduce turnaround times. Thus, the use of a massively parallel system (the Intel Paragon MIMD parallel computer [4]) for the discrete event simulation of k ary 2 cube direct networks is studied in this paper. A few parallel network simulators based on the discrete event simulation technique have been implemented on MIMD and SIMD machines, e.g. 5] This work differs from those in the study of different ....

....process state is calculated; if an LP is in the waiting state, it is determined whether the awaited message has been arrived, and, in this case, the status is changed from waiting to ready. 4 SIMULATOR SPEEDUP The simulator was implemented on the Intel Paragon XP S MIMD machine with 72 PEs [4]. In Figure 3, the achievable speedup for the simulation of a 3232 asynchronous mesh is shown. Speedup is defined as the quotient of the simulator execution time of a fixed size network on i 1 Paragon PEs and the execution time of the same network on two Paragon PEs (due to the restricted memory ....

R. Esser and R. Knecht, Intel Paragon XP/S - Architecture and software environment, Supercomputer, 1993, 121-141.

....to that, interactive processes are executed on the nodes in the service partition. Finally, the nodes in the I O partition are used to connect I O devices. Design of NXLib In the following sections the design of NXLib is introduced. A more detailed presentation can be found in [SLBL93] or [EK93] Virtualization of Paragon nodes A parallel application on a Paragon system consists of two parts. The application processes on the compute partition and the controlling process on one node of the service partition. In the followingdiscussion the term Paragon node (PN) will be referred to as ....

R. Esser and R. Knecht. Intel Paragon XP/S - Architecture and Software Environment. Technical Report KFA-ZAM-IB-9305, Forschungszentrum Julich GmbH, Zentralinstitut fur An gewandte Mathematik, D-52425 Julich, April 1993.

....not only waste local memory resources but also limits scalability in general. OSF 1 AD, the microkernel based parallel operating system for the Intel Paragon, gives an example of this circumstance. In many installations, the pernode memory consumption of OSF 1 AD is about seven to eight megabytes [7]. Thus, in a standard 16 megabytes node configuration, about half of the memory resources are confiscated by the operating system. Although OSF 1 AD implements virtual memory on every node, the user tries to partition the application program (i.e. data) such that it fits entirely into physical ....

R. Esser and R. Knecht. Intel Paragon XP/S---Architecture and Software Environment. In Proceedings of Supercomputer '93, Lecture Notes in Computer Science, Mannheim, Germany, June 24--26 1993. Springer-Verlag.

....independence, applicable to a wide range of MPS. The USM does not impose any network topology. However, each topology requires another routing approach. In the FTMPS project we focus on mesh based architectures. Indeed, this topology covers a wide range of massively parallel systems [8] 7] [3] thanks to its expandability and routing simplicity [11] 2.2 Parsytec GC Series The Parsytec GC series covers a wide range of (massively) parallel computers. The GCel [8] consists of a network of T805 transputers connected in a 2D grid. Statical routing switches and a control network allow ....

Esser R., Knecht R.: Intel Paragon XP/S - Architecture and Software Environment. Proceedings of Supercomputer 93, Mannheim, June 1993.

....to J u;v 1 ) g Figure 3. sketch of the v th row stripe solve model, based on a communication library called NX. Communication is performed using wormhole routing. Messages are split into packets (default length of 1024 bytes) before transmission. For more details on this computer, see [7]. We have used the Paragon system of Universit e de Lyon I, which has 24 computing processors, 4 of them with 32 Mb, the 20 others with 16 Mb. We have implemented in C an algorithm simulating a 2D grid precedence graph of tasks using the SPMD programming paradigm. The core of a task is given by ....

R. Esser, R. Knecht, Intel Paragon XP/S - Architecture and software environment, Internal Report KFA-ZAM-IB-9305, Forschungszentrum Julich, Germany, 1993.

....do overlap. Evaluating communication costs is much harder than for computation costs, and this for many reasons: ffl State of the art DMPCs have dedicated routing facilities, so that the distance of a communication might be less important than the number of conflicts on communication links [4, 6, 20]. ffl Even in a simple case like the tree example, the size of the communications depends upon the distribution of the array and the alignment. Therefore we assume that communication costs are fixed parameters that might be calculated according to some intricate formula, where important ....

R. Esser and R. Knetcht. Intel Paragon XP/S - Architecture and Software Environment. Technical Report KFA-ZAM-IB-9305, Zentralinstitut fur Angewandte Mathematik - Forschungszentrum Julich, April 1993.

....(also called distributed shared memory) machines. In message passing machines, a processor sees only its own local memory. Accessing data residing on a remote node is done by exchanging messages with a processor on this node; this processor will complete this access on its behalf. Intel Paragon [EK93] and Thinking Machines CM5 [CM592] are examples of these machines. Globally shared memory machines, on the other hand, provide a processor with an address space containing all the machine memory. This is done through cache coherent mechanisms that replicate copies of needed data (residing on ....

....Support In this thesis, we concentrate on one important approach for reducing hiding the communication synchronization time through architectural support. Many Industrial and experimental architectures (Intel Paragon, Stanford FLASH, Wisconsin Typhoon, MIT StarT NG, and McGill EARTH [EK93, KOH 94, RLW94, CAA 95, HMT 95] include dedicated hardware for communication and synchronization such that the main processor can concentrate on computation without being distracted by such tasks 4 . The main advantages of this approach are: i) the 3 Since we have not presented ....

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Rudiger Esser and Renate Knecht. Intel paragon XP/S - architecture and software environment. Technical Report KFA-ZAM-IB-9305, Forschungszentrum Julich GmbH, April 1993.

....of jobs. In addition to jobs consisting of a single process, jobs with multiple parallel execution threads must be managed (parallel job) The scheduling algorithm which is used must respect that either all of the processes of a parallel job are in execution or none of them (gang scheduling [3]) This technique avoids unnecessary waiting conditions for results from processes which are currently suspended. The efficiency of a parallel application is hence preserved. 3.2 Consistent Checkpoints As presented in section 2 checkpoint files are the basis of the process migration facility in ....

R. Esser and R. Knecht. Intel Paragon XP/S - Architecture and Software Environment. Technical Report KFA-ZAM-IB-9305, Forschungszentrum Julich GmbH, Zentralinstitut fur Angewandte Mathematik, D-52425 Julich, April 1993.

....5 Related Work In the area of architectural support for communication synchronization, many commercial products and academic projects have intelligent devices either processors or specialized hardware to handle the non computational activities in a node of a parallel machine. In Paragon [EK93] the interface to the interconnection network consists of a message processor, a network interface controller, and two DMA controllers. The message processor is a second i860XP processor operating in parallel and sharing the memory with the application processor. Its task is to perform the ....

Rudiger Esser and Renate Knecht. Intel paragon XP/S - architecture and software environment. Technical Report KFA-ZAM-IB-9305, Forschungszentrum Julich GmbH, April 1993.

....network. This network allows messages to be sent from one PE to another. These messages can be used to allow PEs to share data with one another. The details of such a network are not important to this dissertation. Examples of MIMD machines include the SP2 from IBM [4] and the Paragon from Intel [97, 67]. See Figure 2.1 for a simple schematic of such a machine. 2.1.2 Distributed Memory SIMD Architectures Distributed memory SIMD machines are quite similar to MIMD machines in that they consist of an array of PEs connected by a communication network. However, unlike MIMD machines, the PEs of a SIMD ....

R. Esser and R. Knecht. Intel Paragon XP/S -- architecture and software environment. Technical Report KFA-ZAM-IB-9305, KFA Research Centre, Juelich, April 1993. 146

....to be superscalar. We use a linear model (fi m ) for its performance on vector of size m. In all our experiments we use 64 bit double precision floating point arithmetic. This model corresponds roughly to the currently available commercial machines, such as the Intel iPSC 860 [Dun90] and Paragon [EK93, Int93]. In the remainder of this paper we call fi scal and scal the parameters for the cost of the inversion of the pivot element, the search for the maximum of the vector, the interchange of these two elements, and the scale of the vector by a scalar using the Level 1 BLAS DSCAL function [DCDH90] We ....

R. Esser and R; Knetcht. Intel Paragon XP/S - Architecture and Software Environment. Technical Report KFA-ZAM-IB-9305, Zentralinstitut fur Angewandte Mathematik - Forschungszentrum Julich, April 1993.

....semantics required by Unix standards. 8.1.1 CFS PFS Intel s Concurrent File System [Pie89, Nit92] is frequently cited as the canonical first generation parallel file system. CFS was written for the iPSC family of parallel machines. Its successor, PFS, is similar and was written for the Paragon [EK93, RP95] CFS and PFS provide a simple, Unix like interface to the application. The blocks of a file are declustered across all the disks in round robin order. CFS and PFS extend the conventional Unix interface to provide support for parallel applications by introducing several varieties of shared ....

Rudiger Esser and Renate Knecht. Intel Paragon XP/S --- architecture and software environment. Technical Report KFA-ZAM-IB-9305, Central Institute for Applied Mathematics, Research Center Julich, Germany, April 26 1993.

....architectural support for communication synchronization, many commercial products and academic projects have intelligent devices either processors or specialized hardware to handle the non computational activities in a node of a parallel machine. Examples of these architectures are: Paragon [5], MTA (later called EARTH) 9] Typhoon [16] StarT NG [1] and Flash [12] In the area of expressing parallelism and multithreading constructs at the user level, work has been done in two domains. The first is defining user level multithreading packages, like POSIX Threads [10] for example. The ....

R. Esser and R. Knecht. Intel paragon XP/S - architecture and software environment. Technical Report KFA-ZAM-IB-9305, Forschungszentrum Julich GmbH, Apr. 1993.

....of this technology is to provide architectural support for the minimization of (1) the message startup time and (2) the message latency. However, all these measures are of little value if the operatingsystem architecture for such a hardware organization is inappropriate. For example, OSF 1 AD [4] and Puma [13] both are parallel operating systems for the Paragon machine. One of the main reason that Puma outperforms OSF 1 AD is that the former has been specifically designed to operate in a distributedmemory parallel computer environment, while the latter is mainly a port of a ....

R. Esser and R. Knecht. Intel Paragon XP/S--- Architecture and Software Environment. In Proceedings of Supercomputer '93, Lecture Notes in Computer Science, Mannheim, Germany, June 24--26 1993. Springer-Verlag.

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R. Esser and R. Knecht, Intel Paragon XP/S - Architecture and Software Environment, in: H.W. Meuer, Hrsg., Supercomputer '93, Anwendungen, Architekturen, Trends, Seminar, Mannheim, 24.-26. Juni 1993 (Springer-Verlag, Berlin, 1993) 121-141.

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Esser, R., Knecht, R.: Intel Paragon XP/S - Architecture and Software Environment. In: H.-W. Meuer (ed.): Superconputer '93. Seminar, Mannheim, 24.-26. Juni 1993, Springer-Verlag, Berlin, 1993

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R. Esser and R. Knecht, "Intel Paragon XP/s---Architecture and Software Environment," Proc. Supercomputer '93, Lecture Notes in Computer Science, Springer-Verlag, 1993, pp. 121--141.

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R. Esser and R; Knetcht. Intel Paragon XP/S - Architecture and Software Environment. Technical Report KFA-ZAM-IB-9305, Zentralinstitut fur Angewandte Mathematik - Forschungszentrum Julich, April 1993.

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