V. Mooney and G. De Micheli, "Real-Time Analysis and Priority Scheduler Generation For HardwareSoftware Systems with a Synthesized Run-Time System," Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 605--612, November, 1997. Home/Search Document Details and Download
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Path-Based Edge Activation for Dynamic Run-Time Scheduling - Mooney, III (Correct)
....required, e.g. in the presence of relative timing constraints among hardware tasks. We further assume that some dynamic scheduling is required to handle inexact execution delays, which are certainly present in software tasks, and conditional execution of tasks. The run time scheduler synthesis of [17, 18, 19] assumed that no conditional execution of tasks would occur. Our tool, called Clara2, automates the addition of conditional edges to the original control ow of hardware and software tasks in order to satisfy resource constraints while minimizing worst case execution time (WCET) for the ....
.... gravity sum vector matrix vector multiply matrix vector multiply forward kinematics Figure 1: Robotics Example: Concurrent Control Laws 2 Task Modelling The research here builds on previously reported results; thus, in this section, we brie y summarize the task modelling approach of [16, 17, 18, 19]. Tasks are speci cied in Verilog or C, with one of the tasks designated as the main task. The main task begins execution and calls the other tasks. The main task speci es the overall sequence of tasks in the application (an example of a main task can be seen in Figure 2) From the main task we ....
[Article contains additional citation context not shown here]
V. Mooney and G. De Micheli, \Real Time Analysis and Priority Scheduler Generation for Hardware-Software Systems with a Synthesized Run-Time System," Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD'97), 605-612, 1997.
Optimizing Timed Cosimulation by Hybrid Synchronization - Yoo, Choi (2 citations) (Correct)
....of storage elements (registers or data memory) accessed by a task during the task execution. On the de nition of task we set no restrictions. A task can be a simple function, a star or a galaxy in Ptolemy[4] a CFSM (Codesign Finite State Machine) in POLIS [5] a real time task described in [15], or an object consisting of a variable set and methods in [27] 25] From the implementational point of view, we specify a task as a (set of) code segment(s) in SW (SW task) or a set of components in HW (HW task) The basic idea of task based state saving (TBSS) method is to store only the states ....
V. J. Mooney and G. De Micheli. Real Time Analysis and PriorityScheduler Generation for Hardware-Software Systems with a Synthesized Run-Time System. ##### #### ##### ## ######## ##### ######, pages 605-612, November 1997.
Hardware/Software Co-Design of Run-Time Schedulers for.. - Mooney, III (2000) Self-citation (Mooney De micheli) (Correct)
No context found.
V. Mooney and G. De Micheli, "Real-Time Analysis and Priority Scheduler Generation For HardwareSoftware Systems with a Synthesized Run-Time System," Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 605--612, November, 1997.
Path-Based Edge Activation for Dynamic Run-Time Scheduling - Mooney, III Self-citation (Mooney) (Correct)
....required, e.g. in the presence of relative timing constraints among hardware tasks. We further assume that some dynamic scheduling is required to handle inexact execution delays, which are certainly present in software tasks, and conditional execution of tasks. The run time scheduler synthesis of [17, 18, 19] assumed that no conditional ex ecution of tasks would occur. Our tool, called CLARA2, automates the addition of conditional edges to the original control flow of hardware and software tasks in order to satisfy resource constraints while minimizing worst case execution time (WCET) for the ....
....from robotics. Finally, Section 8 concludes the paper. Ohold2 Ohold Jhold Law: Law: Law: Figure 1: Robotics Example: Concurrent Control Laws 2 Task Modelling The research here builds on previously reported results; thus, in this section, we briefly summarize the task mod elling approach of [16, 17, 18, 19]. Tasks are specificied in Verilog or C, with one of the tasks designated as the main task. The main task begins execution and calls the other tasks. The main task spec ifies the overall sequence of tasks in the application (an example of a main task can be seen in Figure 2) From the main task ....
[Article contains additional citation context not shown here]
V. Mooney and G. De Micheli, "Real Time Analysis and Priority Scheduler Generation for Hardware-Software Systems with a Synthesized Run-Time System," Proceedings of the IEEE In- ternational Conference on Computer-Aided Design (ICCAD'97), 605-612, 1997.
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