W. R. Heller, W. F. Mikhail, and W. E. Donath. Prediction of wiring space requirements for LSI. In Proceedings of the 14th Design Automation Conference, pages 32--42, June 1977. Home/Search Document Not in Database Summary Related Articles Check |
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Optimal Folding Of Standard And Custom Cells - Thanvantri, Sahni (Correct)
....the component Ci is in one row and Ci l is in the next. If the list is folded at Ci and Cj and at no component Ck for i k j, then components Ci l, Cj are in the same row. Suppose the list is folded at Ci. The channel height needed between the rows containing Ci and Ci l may be estimated [HEL77] using the number of nets that have a pin in one of the components C1, Ci as well as in one of the components Ci l, C, Let this height estimate be li, 1 i n. Let l, 0. We study the following folding problems: Standard cell folding to minimize total routing channel area subject to ....
Heller, W. R., W. F. Mikhail, and W. E. Donath," Prediction of Wiring Space Requirements for LSI", 14th Design Automation Conference, pp. 32-42, 1977.
On the Intrinsic Rent Parameter and Spectra-Based.. - Hagen, Kahng.. (1994) (29 citations) (Correct)
....quality, e.g. Feuer s estimates of the average wire lengths are within 23 of the actual values, using a default value of p = 0:720 as the Rent parameter. Wirelength estimates also lie at the heart of the analytic area estimation methods used in synthesis; see, e.g. El Gamal [12] Heller [8], Kurdahi [27] and Sastry [35] We note that other authors have proposed wire length distribution models which do not use Rent s rule. These include Sechen[39] Pedram and Preas[33] and Hamada et al. 19] all of whom estimate interconnection length based on local neighborhood analysis approaches: ....
W. R. Heller et al. Prediction of wiring space requirements for LSI. In Proceedings of the 14th DA Conference, pages 20--22. IEEE/ACM, 1977.
Optimizing Power Using Transformations - Chandrakasan, Potkonjak, Mehra.. (1995) (97 citations) (Correct)
....estimating the interconnect component is a very difficult and challenging task. Driven by yield, floorplanning and synthesis considerations for throughput and area optimization, several elaborate prediction models for total chip and interconnect area have been built and successfully used [30] [31]. However, high level synthesis adds additional requirements on the prediction tools next to accuracy; during the optimization process in high level synthesis, it is necessary to estimate the final cost frequently and therefore computationally intensive models are prohibited, regardless of their ....
W.R. Heller et al. "Prediction of wiring space requirements for LSI", IEEE/ACM Proc. 14th Design Automation Conference, pp. 20-22, 1977.
Interconnection Analysis for Standard Cell Layouts - Massoud Pedram Bryan (Correct)
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W. R. Heller, W. F. Mikhail, and W. E. Donath. Prediction of wiring space requirements for LSI. In Proceedings of the 14th Design Automation Conference, pages 32--42, June 1977.
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