F.J. Kurdahi, A.C. Parker: "Techniques and Area Estimation of VLSI Layouts", IEEE Trans. on CAD, Vol. 8, No. 1, pp. Home/Search Document Not in Database Summary Related Articles Check |
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Optimizing Power Using Transformations - Chandrakasan, Potkonjak, Mehra.. (1995) (97 citations) (Correct)
....accurate, estimating the interconnect component is a very difficult and challenging task. Driven by yield, floorplanning and synthesis considerations for throughput and area optimization, several elaborate prediction models for total chip and interconnect area have been built and successfully used [30], 31] However, high level synthesis adds additional requirements on the prediction tools next to accuracy; during the optimization process in high level synthesis, it is necessary to estimate the final cost frequently and therefore computationally intensive models are prohibited, regardless of ....
F.J. Kurdahi, A.C. Parker: "Techniques and Area Estimation of VLSI Layouts", IEEE Trans. on CAD, Vol. 8, No. 1, pp. 81-92, Jan 1989. Conclusions 27 of 27
Figure 13. Decoupling Capacitance Hierarchy - Board Power Supply (Correct)
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F.J. Kurdahi, A.C. Parker: "Techniques and Area Estimation of VLSI Layouts", IEEE Trans. on CAD, Vol. 8, No. 1, pp.
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