J. Rabaey and M. Potkonjak, "Estimating implementation bounds for real-time application specific circuits," IEEE Trans. Computer-Aided Design, vol. 13, pp. 669--683, June 1994. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Behavioral-Level Synthesis of Heterogeneous BISR.. - Guerra, Potkonjak.. (1998) (1 citation) Self-citation (Rabaey Potkonjak) (Correct)
...., on the necessary amount of hardware of each class is used as the initial allocation. is defined as: where is a minimum bound on the amount of hardware necessary for any non faulttolerant implementation and is the number of faults. For each hardware class, relaxed based scheduling techniques [20] are used to derive an estimate of . The equation for can be understood by observing that any implementation requires at least units, and since up to units of type can be bad, at least units are needed. If the initial allocation fails, the allocation expansion phase is entered, where new ....
....verified heuristics for the stress function are described. 1) Minimum bounds stress, MB: By experimental observation, operations of type whose relaxed scheduling minimum hardware bound ( is close to its absolute minimum hardware bound ( are difficult to schedule. The absolute minimum bound [20] for hardware type is: NumNodes duration AvailableTime , where NumNodes is the number of nodes that are executed on hardware of type , duration is the clock cycle duration of the hardware, AvailableTime is the sample period in clock cycles, and is the number of allowable faulty units. The minimum ....
[Article contains additional citation context not shown here]
J. Rabaey and M. Potkonjak, "Estimating implementation bounds for real-time application specific circuits," IEEE Trans. Computer-Aided Design, vol. 13, pp. 669--683, June 1994.
Behavioral-Level Synthesis of Heterogeneous BISR.. - Guerra, Potkonjak.. (1993) (1 citation) Self-citation (Rabaey Potkonjak) (Correct)
....amount of hardware of each class j is used as the initial allocation. M j is defined as: where m j is a minimum bound on the amount of hardware j necessary for any non fault tolerant implementation and K is the number of faults. For each hardware class, j, relaxed based scheduling techniques [Rab94] are used to derive an estimate of m j . The equation for M j can be understood by observing that any implementation requires at least m j units, and since up to K units of type j can be bad, at least (m j K) units are needed. 4.2.2 Expansion Phase If the initial allocation fails, the ....
....verified heuristics for the stress function are described. 1. Minimum bounds stress, MB: By experimental observation, operations of type j whose relaxed scheduling minimum hardware bound (R) is close to its absolute minimum hardware bound (X) are difficult to schedule. The absolute minimum bound [Rab94] for hardware type j is: where NumNodes j is the number of nodes that are executed on hardware of type j, duration j is the clock cycle duration of the hardware, AvailableTime is the sample period in clock cycles, and K is the number of allowable faulty units. The minimum bounds stress for ....
[Article contains additional citation context not shown here]
J. Rabaey and M. Potkonjak, "Estimating Implementation Bounds for Real-Time Application Specific Circuits, " IEEE Transactions on CAD, Vol. 13, No. 6, pp. 669-683, 1994.
Optimizing Power Using Transformations - Chandrakasan, Potkonjak, Mehra.. (1995) (97 citations) Self-citation (Rabaey Potkonjak) (Correct)
.... components: C total = C exu C registers C interconnect C control (EQ 5) The capacitance estimation is built on top of an existing estimation routine in HYPER that determines bounds and activity of various execution, register and interconnect components as well as the implementation area [28], 29] The details of the capacitance estimation routines are described below. 5.1.1 Execution Units The capacitance switched by the execution units is estimated by multiplying (over all types of operations) the number of times the operation is performed per sample period and the average ....
....receives the clock and clock inverse every control cycle. In the hardware model used, the clock inverse is generated in the local controllers and fed to the execution units. The HYPER high level synthesis system provides a lower bound on the number of execution units within as accuracy of 10 [28]. The lower bound on the busses tracks the actual number of busses closely and the maximum number of busses tracks the total number of bus accesses. The numbers predicted by HYPER were therefore used in building the correlation model. The fit function obtained for the total number of output ....
J. Rabaey and M. Potkonjak, "Estimating Implementation Bounds for Real Time Application Specific Circuits", European Solid-State Circuits Conference, Milano, Italy, pp. 201-204, September 11-13, 1991.
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